Abstract: Devices and techniques for packet arbitration for buffered packets in a network device are described herein. A packet can be received at an input of the network device. The packet can be placed in a buffer for the input and a characteristic of the packet can be obtained. A record for the packet, that includes the characteristic, is written into a data structure that is independent of the buffer. Arbitration, based on the characteristic of the packet in the record, can then be performed among multiple packets to select a next packet from the buffer for delivery to an output.

Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing the size of packet headers by using a single field to encode multiple elements. Instead of including separate fields for each element, one or more encoded fields may be used, each of which is decoded to determine two or more values for the data packet. A receiving device decodes the encoded data field to retrieve the two or more values.

Abstract: Devices and techniques for variable pipeline length in a barrel-multithreaded processor are described herein. A completion time for an instruction can be determined prior to insertion into a pipeline of a processor. A conflict between the instruction and a different instruction based on the completion time can be detected. Here, the different instruction is already in the pipeline and the conflict detected when the completion time equals the previously determined completion time for the different instruction. A difference between the completion time and an unconflicted completion time can then be calculated and completion of the instruction delayed by the difference.

Abstract: Devices and techniques for managing hazards in a memory controller are described herein. The memory controller can receive a memory request that includes a base memory address. An index can be computed from the base memory address and a lookup, using the index, can be performed to find a lock. When the lock is found, the memory controller can store the memory request in a buffer that corresponds to the lock. In response to a signal to clear the lock, the memory controller removes the memory request from the buffer and performs the memory request.

Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

Abstract: Implementations of the present disclosure are directed to systems and methods for processing headers that support multiple protocols. A header of a packet includes a bridge type (BTYPE) field that indicates the protocol of the packet. A command field of the packet is interpreted differently based on the value of the BTYPE field. Among the benefits of implementations of the present disclosure is that a single network may be used to carry packets of different protocols without the overhead of encapsulation.

Abstract: A transmitting device generates multiple small packets for a large packet and transmits them to a receiving device. Routing devices forward the multiple small packets to the receiving device. Each of the smaller packets, except the last packet, has a sequence indicator set. As a result, the receiving device is able to determine that each of the smaller packets is part of a larger packet and buffer the smaller packets or their payloads. When the last packet is received, the larger packet is complete and may be processed by the receiving device. The routing devices delay requests from other transmitting devices to transmit data to the receiving device until the last packet is sent to the receiving device. The routing devices may continue to route traffic to the receiving device on all virtual channels other than a virtual channel being used for the large packet.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.

Abstract: A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may be coupled to each other via an interface network, and may include multiple chiplets. The multiple hardware transceivers, with at least one transceiver included in or coupled to a respective electronic device of the multiple electronic devices, may each be configured to receive data packets from a source device. The data packets may each include a path field including path information indicating a path to a destination device and a bridge-type field including bridge-type information indicating a type of the path information in the path field. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using the path information and the bridge-type information of each received data packet.

Abstract: A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.

Abstract: Devices and techniques for managing hazards in a memory controller are described herein. The memory controller can receive a memory request that includes a base memory address. An index can be computed from the base memory address and a lookup, using the index, can be performed to find a lock. When the lock is found, the memory controller can store the memory request in a buffer that corresponds to the lock. In response to a signal to clear the lock, the memory controller removes the memory request from the buffer and performs the memory request.

Abstract: Disclosed in some examples are methods, systems, memory controllers, devices, and machine-readable mediums which minimize this stall time by returning a memory write acknowledgement once a write command has been selected by the memory controller input multiplexor rather than when the memory write command has been performed. Because the memory controller enforces an ordering to memory once the packet has been selected at an input multiplexor, ordering of prior and subsequent requests to the same address location are preserved and providing the response early allows the processor to continue its operations earlier without any harmful effects.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.

Abstract: Methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

Abstract: Implementations of the present disclosure are directed to systems and methods for flow control using a multiple flit interface. A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. The amount of buffer space used by the receiver to store the packet is determined by the number of transfer cycles used to receive the packet, not the number of flits comprising the packet. This is enabled by having the buffer be as wide as the bus. The receiver returns credits to the sender based on the number of buffer rows used to store the received packet, not the number of flits comprising the packet.

Abstract: Devices and techniques for packet arbitration for buffered packets in a network device are described herein. A packet can be received at an input of the network device. The packet can be placed in a buffer for the input and a characteristic of the packet can be obtained. A record for the packet, that includes the characteristic, is written into a data structure that is independent of the buffer. Arbitration, based on the characteristic of the packet in the record, can then be performed among multiple packets to select a next packet from the buffer for delivery to an output.

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Abstract: A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. A write enable mask allows a wide data field to be used even when a smaller amount of data is to be written. A novel data packet uses a combined write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode may be selected based on another value in the data packet.

Abstract: A transmitting device generates multiple small packets for a large packet and transmits them to a receiving device. Routing devices forward the multiple small packets to the receiving device. Each of the smaller packets, except the last packet, has a sequence indicator set. As a result, the receiving device is able to determine that each of the smaller packets is part of a larger packet and buffer the smaller packets or their payloads. When the last packet is received, the larger packet is complete and may be processed by the receiving device. The routing devices delay requests from other transmitting devices to transmit data to the receiving device until the last packet is sent to the receiving device. The routing devices may continue to route traffic to the receiving device on all virtual channels other than a virtual channel being used for the large packet.