Abstract: Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.

Abstract: Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction.

Abstract: Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.

Abstract: Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction.

Abstract: An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Abstract: It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.

Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correc soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: An aspect includes a method for receiving a memory allocation request for a logical partition. Partition mirroring is enabled for the logical partition. Unscrubbed memory is allocated to both a first and a second copy of the logical partition, with the second copy of the logical partition mirroring the first copy of the logical partition. Scrubbing of the first and second copy of the logical partitions is initiated. Subsequent to initiating the scrubbing one of the first and second copy of the logical partition is selected and partition mirroring is disabled for the logical partition. The first copy of the logical partition is deallocated based on selecting the second copy of the logical partition. The second copy of the logical partition is deallocated based on selecting the first copy of the logical partition.

Abstract: An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.

Abstract: An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.

Abstract: An aspect includes a method for receiving a memory allocation request for a logical partition. Partition mirroring is enabled for the logical partition. Unscrubbed memory is allocated to both a first and a second copy of the logical partition, with the second copy of the logical partition mirroring the first copy of the logical partition. Scrubbing of the first and second copy of the logical partitions is initiated. Subsequent to initiating the scrubbing one of the first and second copy of the logical partition is selected and partition mirroring is disabled for the logical partition. The first copy of the logical partition is deallocated based on selecting the second copy of the logical partition. The second copy of the logical partition is deallocated based on selecting the first copy of the logical partition.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.

Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: An aspect includes a method for receiving a memory allocation request for a logical partition. Partition mirroring is enabled for the logical partition. Unscrubbed memory is allocated to both a first and a second copy of the logical partition, with the second copy of the logical partition mirroring the first copy of the logical partition. Scrubbing of the first and second copy of the logical partitions is initiated. Subsequent to initiating the scrubbing one of the first and second copy of the logical partition is selected and partition mirroring is disabled for the logical partition. The first copy of the logical partition is deallocated based on selecting the second copy of the logical partition. The second copy of the logical partition is deallocated based on selecting the first copy of the logical partition. The copy that is selected will continue to be scrubbed on a periodic based.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.