Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.

Abstract: An aspect includes a method for receiving a memory allocation request for a logical partition. Partition mirroring is enabled for the logical partition. Unscrubbed memory is allocated to both a first and a second copy of the logical partition, with the second copy of the logical partition mirroring the first copy of the logical partition. Scrubbing of the first and second copy of the logical partitions is initiated. Subsequent to initiating the scrubbing one of the first and second copy of the logical partition is selected and partition mirroring is disabled for the logical partition. The first copy of the logical partition is deallocated based on selecting the second copy of the logical partition. The second copy of the logical partition is deallocated based on selecting the first copy of the logical partition. The copy that is selected will continue to be scrubbed on a periodic based.

Abstract: An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Abstract: In a method for designating cooling fan control management in a computing system, a processor causes one or more cooling fans to be managed by a first process, wherein the first process utilizes a first set of temperature sensors of a plurality of temperature sensors. A processor receives temperature data from a first set of temperature sensors. A processor determines a second process to manage the one or more cooling fans, based on the received temperature data from the first set of temperature sensors, wherein the second process utilizes a second set of temperature sensors of the plurality of temperature sensors.

Abstract: A computer-implemented method includes capping the amount of power available to each of a plurality of compute nodes, and managing power allocation among subsystems within each of the compute nodes according to the requirements of workloads assigned to each of the compute nodes. The method further comprises reporting an actual performance level and performance capability for each subsystem within each of the plurality of compute nodes, and monitoring parametric data for a particular workload. A target compute node is identified from among the compute nodes, wherein the target compute node would be capable of performing the particular workload if power was reallocated from a first subsystem to a second subsystem within the target compute node. The particular workload is then assigned to the target compute node. Optionally, assigning the particular workload may include migrating the workload to the target compute node from another of the compute nodes.

Abstract: A memory module determines that the memory module is connected to a memory module connector. The memory module receives the connector ID from the connector and communicates, to the connector, a memory module ID associated with the memory module. A connector-module ID token is generated using the connector ID and the memory module ID. It is determined that the connector-module ID token was not received from the connector within a predetermined time window. Data on the memory module is erased in response to not receiving the connector-module ID.

Abstract: An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: A memory module contains a set of contacts configured to contact a second set of contacts on a memory module connector when the memory module is removed from the connector. The contacts on the connector can be activated. The memory module is configured to erase data on the memory module in response to the set of contacts on the memory module contacting the set of contacts on the connector when the set of contacts on the connector is activated.

Abstract: In a method for designating cooling fan control management in a computing system, a processor causes one or more cooling fans to be managed by a first process, wherein the first process utilizes a first set of temperature sensors of a plurality of temperature sensors. A processor receives temperature data from a first set of temperature sensors. A processor determines a second process to manage the one or more cooling fans, based on the received temperature data from the first set of temperature sensors, wherein the second process utilizes a second set of temperature sensors of the plurality of temperature sensors.

Abstract: A memory module contains a set of contacts configured to contact a second set of contacts on a memory module connector when the memory module is removed from the connector. The contacts on the connector can be activated. The memory module is configured to erase data on the memory module in response to the set of contacts on the memory module contacting the set of contacts on the connector when the set of contacts on the connector is activated.

Abstract: A memory module contains a set of contacts configured to contact a second set of contacts on a memory module connector when the memory module is removed from the connector. The contacts on the connector can be activated. The memory module is configured to erase data on the memory module in response to the set of contacts on the memory module contacting the set of contacts on the connector when the set of contacts on the connector is activated.

Abstract: A memory module determines that the memory module is connected to a memory module connector. The memory module receives the connector ID from the connector and communicates, to the connector, a memory module ID associated with the memory module. A connector-module ID token is generated using the connector ID and the memory module ID. It is determined that the connector-module ID token was not received from the connector within a predetermined time window. Data on the memory module is erased in response to not receiving the connector-module ID.

Abstract: A memory module determines that the memory module is connected to a memory module connector. The memory module receives the connector ID from the connector and communicates, to the connector, a memory module ID associated with the memory module. A connector-module ID token is generated using the connector ID and the memory module ID. It is determined that the connector-module ID token was not received from the connector within a predetermined time window. Data on the memory module is erased in response to not receiving the connector-module ID.

Abstract: A memory module contains a set of contacts configured to contact a second set of contacts on a memory module connector when the memory module is removed from the connector. The contacts on the connector can be activated. The memory module is configured to erase data on the memory module in response to the set of contacts on the memory module contacting the set of contacts on the connector when the set of contacts on the connector is activated.

Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.

Abstract: A memory module determines that the memory module is connected to a memory module connector. The memory module receives the connector ID from the connector and communicates, to the connector, a memory module ID associated with the memory module. A connector-module ID token is generated using the connector ID and the memory module ID. It is determined that the connector-module ID token was not received from the connector within a predetermined time window. Data on the memory module is erased in response to not receiving the connector-module ID.

Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.

Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.