Patents by Inventor Tony Mai
Tony Mai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140225651Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: Conversant Intellectual Property Management Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Patent number: 8704569Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: December 18, 2012Date of Patent: April 22, 2014Assignee: MOSAID Technologies IncorporatedInventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Patent number: 8503598Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: GrantFiled: June 26, 2012Date of Patent: August 6, 2013Assignee: MOSAID Technologies IncorporatedInventor: Tony Mai
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Publication number: 20120306548Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: ApplicationFiled: June 26, 2012Publication date: December 6, 2012Applicant: MOSAID Technologies IncorporatedInventor: Tony Mai
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Patent number: 8218707Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: GrantFiled: December 16, 2009Date of Patent: July 10, 2012Assignee: Mosaid Technologies IncorporatedInventor: Tony Mai
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Patent number: 8035434Abstract: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.Type: GrantFiled: March 30, 2010Date of Patent: October 11, 2011Assignee: MOSAID Technologies IncorporatedInventor: Tony Mai
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Publication number: 20100182059Abstract: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.Type: ApplicationFiled: March 30, 2010Publication date: July 22, 2010Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: TONY MAI
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Patent number: 7761831Abstract: An integrated power and clock grid which is capable of being placed and routed using ASIC software design tools. The integrated grid comprises three types of grid unit cells having power rails and clock lines. The power rails and clock lines comprise different orientations in the different grid unit cells.Type: GrantFiled: December 29, 2005Date of Patent: July 20, 2010Assignee: MOSAID Technologies IncorporatedInventors: Tony Mai, Bruce Millar, Susan Coleman, Seanna Pike
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Publication number: 20100109722Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: ApplicationFiled: December 16, 2009Publication date: May 6, 2010Applicant: MOSAID Technologies IncorporatedInventor: Tony Mai
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Patent number: 7705642Abstract: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.Type: GrantFiled: February 8, 2007Date of Patent: April 27, 2010Assignee: Mosaid Technologies IncorporatedInventor: Tony Mai
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Patent number: 7656988Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: GrantFiled: December 2, 2008Date of Patent: February 2, 2010Assignee: MOSAID Technologies, Inc.Inventor: Tony Mai
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Patent number: 7532050Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: October 4, 2007Date of Patent: May 12, 2009Assignee: MOSAID Technologies, Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Publication number: 20090086876Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: ApplicationFiled: December 2, 2008Publication date: April 2, 2009Applicant: MOSAID Technologies, Inc.Inventor: Tony Mai
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Patent number: 7477716Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: GrantFiled: August 25, 2003Date of Patent: January 13, 2009Assignee: MOSAID Technologies, Inc.Inventor: Tony Mai
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Publication number: 20080191782Abstract: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Inventor: Tony Mai
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Publication number: 20080030247Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: October 4, 2007Publication date: February 7, 2008Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Patent number: 7285997Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: January 29, 2007Date of Patent: October 23, 2007Assignee: Mosaid Technologies, Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Publication number: 20070157144Abstract: An integrated power and clock grid which is capable of being placed and routed using ASIC software design tools. The integrated grid comprises three types of grid unit cells having power rails and clock lines. The power rails and clock lines comprise different orientations in the different grid unit cells.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Tony Mai, Bruce Millar, Susan Coleman, Seanna Pike
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Publication number: 20070120587Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: January 29, 2007Publication date: May 31, 2007Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Patent number: RE43947Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: May 11, 2011Date of Patent: January 29, 2013Assignee: Mosaid Technologies IncorporatedInventors: Dieter Haerle, Tony Mai, Peter Vlasenko