Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14?), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

Abstract: A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a boron-doped further silicon layer over the resultant structure; forming dielectric spacers on the trench sidewalls; filling the trench with emitter material; exposing polysilicon regions outside the trench side walls by selectively removing the sacrificial layer; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing

Abstract: A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a boron-doped further silicon layer over the resultant structure; forming dielectric spacers on the trench sidewalls; filling the trench with emitter material; exposing polysilicon regions outside the trench side walls by selectively removing the sacrificial layer; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing

Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14?), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

Abstract: Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material.

Abstract: A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.

Abstract: An electronic device comprising a generator for generating a stream of charge carriers. The generator comprises a bipolar transistor having an emitter region, a collector region and a base region oriented between the emitter region and the collector region, and a controller for controlling exposure of the bipolar transistor to a voltage in excess of its open base breakdown voltage (BVCEO) such that the emitter region generates the stream of charge carriers from a first area being smaller than the emitter region surface area. The electronic device may further comprise a material arranged to receive the stream of charge carriers for triggering a change in a property of said material, the emitter region being arranged between the base region and the material.

Abstract: A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Abstract: Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively remo

Abstract: A bipolar transistor is fabricated having a collector (52) in a substrate (1) and a base (57, 58) and an emitter (59) formed over the substrate. The base has a stack region (57) which is laterally separated from the emitter (59) by an electrically insulating spacer (71). The insulating spacer (71) has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a ?-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.

Abstract: Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.

Abstract: Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.

Abstract: A device (100) for generating an output signal (So) having substantially same or increased output frequency compared to an input frequency of an input signal (Si), the device (100) comprising: a bipolar transistor (102) having a base (B), a collector (C), and an emitter (E); a control unit (104) adapted for controlling application of the input signal (Si) to the base (B) and adapted for controlling application of a collector-emitter voltage between the collector (C) and the emitter (E) in a manner for operating the bipolar transistor (102) in a snap-back regime to obtain a non-linear collector current characteristic to thereby generate the output signal (So) having the substantially same or increased output frequency resulting from a steeply rising collector current.

Abstract: Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor.

Abstract: A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.

Abstract: A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT.

Abstract: According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter.

Abstract: A device (100) for generating an output signal (So) having substantially same or increased output frequency compared to an input frequency of an input signal (Si), the device (100) comprising: a bipolar transistor (102) having a base (B), a collector (C), and an emitter (E); a control unit (104) adapted for controlling application of the input signal (Si) to the base (B) and adapted for controlling application of a collector-emitter voltage between the collector (C) and the emitter (E) in a manner for operating the bipolar transistor (102) in a snap-back regime to obtain a non-linear collector current characteristic to thereby generate the output signal (So) having the substantially same or increased output frequency resulting from a steeply rising collector current.