Abstract: A flow channel type heat dissipating fin set is formed by a plurality of metal pieces. Each metal piece comprises a body; and a connecting piece installed on the body having one or more connecting pieces punched from the body; the connecting piece being protruded from one side of the body; a via hole being formed on the body; and buckles and buckling holes being formed on the body. The metal pieces are combined by buckling the buckles and buckling holes so that the metal pieces are continuously buckled and stacked as a heat dissipating fin set; and via holes on the bodies of the metal pieces are formed as longitudinal flow channels. Thus, a flow channel type heat dissipating fin set is formed.

Abstract: A method for manufacturing a flash memory device with dual floating gates is disclosed. The method use a self-align etching technique to form dual floating gates by using dual spacers as masks. First of all, a semiconductor substrate having a first insulating layer thereon and a first conductive layer formed over the first insulating layer is provided. Then a second insulating layer is formed and patterned to etch to form a trench therein. Next a dielectric layer is deposited and anisotropically etched to form dual spacers in the trench. After removing the second insulating layer, etching the first conductive layer to expose the first insulating layer, and removing the spacers sequentially, dual floating gates are formed.

Abstract: A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.