Patents by Inventor Tony Wang

Tony Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6382307
    Abstract: A device for forming a heat dissipating fin set comprises a heat tube made of copper, and at least one heat dissipating fin set made of metal. Each fin in the heat dissipating fin set having a though hole. One side of the though hole is extended with a combining portion. A slender hole with a smaller diameter is formed on an upper edge of the though hole; the heat dissipating fin set being engaged to the heat tube through the though holes. A metal wire selected from silver, tin or copper is arranged into the slender holes at an upper edge of fin in the heat dissipating fin set; and then the heat tube and heat dissipating fin set are combined by heat melting. Thereby, a device for forming a heat dissipating fin set with a heat resistor without any interface and having a preferred heat conductance is formed.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: May 7, 2002
    Assignee: Chaun-Choung Technology Corp.
    Inventors: Tony Wang, Quan Lee
  • Patent number: 6352908
    Abstract: A method of forming an isolation structure includes the steps of: providing a silicon substrate; forming an upper pad oxide layer superjacent a top surface of the substrate, and a lower pad oxide layer subjacent a bottom surface of the substrate; forming a nitride masking layer superjacent the upper pad oxide layer, and a lower pad silicon nitride layer subjacent the lower pad oxide layer; patterning and etching the nitride masking layer to expose a portion of the upper pad oxide layer; applying a first etching solution to the exposed portion of the upper pad oxide layer to expose a portion of the substrate substantially defining the boundaries of an active area, and simultaneously forming an undercut cavity by removing a portion of the upper pad oxide layer under the exposed edges of the nitride masking layer surrounding the exposed portion of the substrate; performing an oxidation process to form an etching stop layer over the exposed portion of the substrate and in the undercut cavity, the oxidation proces
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: March 5, 2002
    Assignee: Mosel Vitelic, Inc.
    Inventors: Wei-Sheng King, Tso-Chun Tony Wang
  • Patent number: 6340056
    Abstract: A flow channel type heat dissipating fin set is formed by a plurality of metal pieces. Each metal piece comprises a body; and a connecting piece installed on the body having one or more connecting pieces punched from the body; the connecting piece being protruded from one side of the body; a via hole being formed on the body; and buckles and buckling holes being formed on the body. The metal pieces are combined by buckling the buckles and buckling holes so that the metal pieces are continuously buckled and stacked as a heat dissipating fin set; and via holes on the bodies of the metal pieces are formed as longitudinal flow channels. Thus, a flow channel type heat dissipating fin set is formed.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: January 22, 2002
    Assignee: Chaun-Choung Technology Corp.
    Inventors: Meng-Cheng Huang, Tony Wang
  • Patent number: 6271090
    Abstract: A method for manufacturing a flash memory device with dual floating gates is disclosed. The method use a self-align etching technique to form dual floating gates by using dual spacers as masks. First of all, a semiconductor substrate having a first insulating layer thereon and a first conductive layer formed over the first insulating layer is provided. Then a second insulating layer is formed and patterned to etch to form a trench therein. Next a dielectric layer is deposited and anisotropically etched to form dual spacers in the trench. After removing the second insulating layer, etching the first conductive layer to expose the first insulating layer, and removing the spacers sequentially, dual floating gates are formed.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: August 7, 2001
    Assignee: Macronix International Co., Ltd.
    Inventors: Chong-Jen Huang, Hsin-Huei Chen, Lenvis Liu, Tony Wang, Frank Chiou
  • Patent number: 6251722
    Abstract: A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: June 26, 2001
    Assignee: Mosel Vitelic Inc.
    Inventors: Houng-chi Wei, Tso-chun Tony Wang
  • Patent number: D281538
    Type: Grant
    Filed: May 23, 1983
    Date of Patent: November 26, 1985
    Inventor: Tony Wang