Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.

Abstract: A buffer for converting sinusoidal waves to square waves with reduced phase noise is described herein. The buffer shunts current from the outputs of a differential amplifier during sinusoidal state transition periods at the differential amplifier inputs to increase the finite slope of square wave transition periods of the output square wave. More particularly, a sinusoidal wave having alternating peaks and valleys connected by sinusoidal state transition periods is applied to differential inputs of a differential amplifier to generate a square wave at the differential outputs, where the output square wave comprises alternating high and low states connected by square wave state transition periods having a finite slope. The output square wave is shaped to increase the finite slope of the square wave transition periods by providing additional paths between the differential outputs and ground that shunt current from the differential amplifier during the sinusoidal state transition periods.

Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.

Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.

Abstract: An electronic circuit comprises at least two transistors coupled in parallel, wherein the second transistor channel length is configured such that the threshold voltage of the second transistor is at a peak on a threshold voltage versus channel lengths curve arising from reverse short channel effects for a given semiconductor process. The first transistor is biased with a first gate-source voltage and a first drain-source voltage. The second transistor is biased with a second gate-source voltage and a second drain-source voltage. The first and second gate-source voltages are offset from each other by a gate-source voltage offset. The first and second drain-source voltages are offset from each other by a drain-source voltage offset. These bias conditions result in the transistors operating in different regions so that the second and third-order nonlinearities of the transistors substantially cancel each other out simultaneously.

Abstract: A buffer for converting sinusoidal waves to square waves with reduced phase noise is described herein. The buffer shunts current from the outputs of a differential amplifier during sinusoidal state transition periods at the differential amplifier inputs to increase the finite slope of square wave transition periods of the output square wave. More particularly, a sinusoidal wave having alternating peaks and valleys connected by sinusoidal state transition periods is applied to differential inputs of a differential amplifier to generate a square wave at the differential outputs, where the output square wave comprises alternating high and low states connected by square wave state transition periods having a finite slope. The output square wave is shaped to increase the finite slope of the square wave transition periods by providing additional paths between the differential outputs and ground that shunt current from the differential amplifier during the sinusoidal state transition periods.

Abstract: A sub-threshold transistor bridge circuit for use in detecting the signal level of an input radio-frequency signal is disclosed. In an exemplary embodiment each branch of the sub-threshold transistor bridge circuit comprises a transistor configured to operate in the sub-threshold region over a predetermined range of input signal levels. An input radio-frequency signal applied to a first pair of opposing corners of the bridge circuit yields a bridge output signal at the remaining pair of opposing corners that has a low-frequency component substantially proportional to the squared-amplitude of the envelope of the input radio-frequency signal. Also disclosed are various detector circuits including a sub-threshold transistor bridge circuit, as well as methods for detecting a signal level for an radio-frequency signal using a sub-threshold transistor bridge.

Abstract: The power level of an RF signal is detected using a circuit having relatively low DC offset, high dynamic range, small frequency and temperature dependence and low flicker noise. According to one embodiment, the power detector circuit comprises a chain of amplifiers and a passive mixer. The chain of amplifiers converts the RF input signal to a supply-limited RF square wave signal. The passive mixer passively mixes the supply-limited RF square wave signal with the RF input signal and in response generates a rectified output signal that tracks the amplitude of the RF input signal.

Abstract: An electronic circuit (10) comprises at least two transistors (T12, T14) coupled in parallel, wherein the second transistor channel length is configured such that the threshold voltage of the second transistor (T14) is at a peak on a threshold voltage versus channel lengths curve arising from reverse short channel effects for a given semiconductor process. The first transistor (T12) is biased with a first gate-source voltage and a first drain-source voltage. The second transistor (T14) is biased with a second gate-source voltage and a second drain-source voltage. The first gate-source voltage and the second gate-source voltage are offset from each other by a gate-source voltage offset and the first drain-source voltage and the second drain-source voltage are offset from each other by a drain-source voltage offset.

Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.

Abstract: A sub-threshold transistor bridge circuit for use in detecting the signal level of an input radio-frequency signal is disclosed. In an exemplary embodiment each branch of the sub-threshold transistor bridge circuit comprises a transistor configured to operate in the sub-threshold region over a predetermined range of input signal levels. An input radio-frequency signal applied to a first pair of opposing corners of the bridge circuit yields a bridge output signal at the remaining pair of opposing corners that has a low-frequency component substantially proportional to the squared-amplitude of the envelope of the input radio-frequency signal. Also disclosed are various detector circuits including a sub-threshold transistor bridge circuit, as well as methods for detecting a signal level for an radio-frequency signal using a sub-threshold transistor bridge.

Abstract: A method of implementing a transistor circuit comprises coupling first and second transistors in parallel, wherein the first transistor has a channel length corresponding to a peak in the transistor's voltage threshold curve arising from reverse short channel effects, and the second transistor has a longer channel length and, therefore, a lower threshold voltage. Exploiting reverse short channel effects in this manner enables the implementation of “composite” transistor circuits that exhibit improved linearity.

Abstract: The power level of an RF signal is detected using a circuit having relatively low DC offset, high dynamic range, small frequency and temperature dependence and low flicker noise. According to one embodiment, the power detector circuit comprises a chain of amplifiers and a passive mixer. The chain of amplifiers converts the RF input signal to a supply-limited RF square wave signal. The passive mixer passively mixes the supply-limited RF square wave signal with the RF input signal and in response generates a rectified output signal that tracks the amplitude of the RF input signal.

Abstract: An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2?; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath the LDMOS gate region, the channel interconnecting the LDMOS source and drain regions and having a laterally graded doping concentration. In order to obtain a lower parasitic capacitance coupling from the gate semiconductor region, the gate semiconductor layer region is provided with a laterally graded net doping concentration (P+N+; N+N?). A method for fabrication of the inventive LDMOS transistor device is further disclosed.

Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, has a transistor (11; 51), preferably a power LDMOS transistor, and a spiral inductor (12; 26; 41; 52, 53), preferably an RF blocking inductor. The spiral inductor is arranged on top of the transistor, whereby an electromagnetic coupling between the spiral inductor and the transistor is not typically possible to avoid. However, the transistor has a finger type layout (13a-k, 14a-f) to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit is strongly reduced by such an arrangement.

Abstract: A time delay line comprises a plurality of delay elements connected in series. Each delay element comprises one or more transistors that exhibit a reverse short channel effect at channel lengths within a certain range. The transistors are configured to have a channel length in the certain range in order to reduce time delay sensitivity to process variations.

Abstract: An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2?; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath the LDMOS gate region, the channel interconnecting the LDMOS source and drain regions and having a laterally graded doping concentration. In order to obtain a lower parasitic capacitance coupling from the gate semiconductor region, the gate semiconductor layer region is provided with a laterally graded net doping concentration (P+N+; N+N?). A method for fabrication of the inventive LDMOS transistor device is further disclosed.

Abstract: A monolithically integrated bipolar transistor has an SOI substrate, a collector region in the SOI substrate, a base layer region on top of and in contact with the collector region, and an emitter layer region on top of and in contact with the base layer region, wherein the collector, base layer, and emitter layer regions are provided with separate contact regions. Further, a region of an insulating material, preferably an oxide or nitride, is provided in the base layer region, in the emitter layer region, or between the base and emitter layer regions, wherein the insulating region extends laterally at a fraction of a width of the base and emitter layer regions to reduce an effective width of the bipolar transistor to thereby eliminate any base push out effects that would otherwise occur.

Abstract: An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2?; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath the LDMOS gate region, the channel interconnecting the LDMOS source and drain regions and having a laterally graded doping concentration. In order to obtain a lower parasitic capacitance coupling from the gate semiconductor region, the gate semiconductor layer region is provided with a laterally graded net doping concentration (P+N+; N+N?). A method for fabrication of the inventive LDMOS transistor device is further disclosed.

Abstract: An integrated LDMOS transistor comprises a semiconductor substrate (11), an LDMOS gate region (17), LDMOS source (14) and drain (15) regions, and a channel region (13) arranged beneath the LDMOS gate region, where the channel region interconnects the LDMOS source and drain regions. The LDMOS gate region comprises first (18a) and second (18b) gate insulation layer regions, a centrally located gate-dividing insulation region (19) provided between the first and second gate insulation layer regions, and first (20a) and second (20b) individual gate conducting layer regions, each being provided on top of a respective one of the first and second gate insulation layer regions, and each being an etched outside spacer region at the centrally located insulation layer region.