Abstract: A monolithically integrated microwave frequency high power amplifier device comprises a plurality of transistors connected in a load modulation configuration wherein the number of the transistors that is operational depends on the drive level. The transistors have each a finger type layout, where fingers from different ones of the transistors are interleaved. The sources of the plurality of transistors are typically interconnected, whereas the gates of the transistors have separate connections for connection to separate package leads. Similarly, the drains of the transistors have separate connections for connection to separate package leads. Advantageously, an LC-based passive network performs a power combining operation of the amplifier device.

Abstract: A method of implementing a transistor circuit comprises coupling first and second transistors in parallel, wherein the first transistor has a channel length corresponding to a peak in the transistor's voltage threshold curve arising from reverse short channel effects, and the second transistor has a longer channel length and, therefore, a lower threshold voltage. Exploiting reverse short channel effects in this manner enables the implementation of “composite” transistor circuits that exhibit improved linearity.

Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, has a transistor (11; 51), preferably a power LDMOS transistor, and a spiral inductor (12; 26; 41; 52, 53), preferably an RF blocking inductor. The spiral inductor is arranged on top of the transistor, whereby an electromagnetic coupling between the spiral inductor and the transistor is not typically possible to avoid. However, the transistor has a finger type layout (13a-k, 14a-f) to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit is strongly reduced by such an arrangement.

Abstract: A monolithically integrated microwave frequency high power amplifier device comprises a plurality of transistors connected in a load modulation configuration wherein the number of the transistors that is operational depends on the drive level. The transistors have each a finger type layout, where fingers from different ones of the transistors are interleaved. The sources of the plurality of transistors are typically interconnected, whereas the gates of the transistors have separate connections for connection to separate package leads. Similarly, the drains of the transistors have separate connections for connection to separate package leads. Advantageously, an LC-based passive network performs a power combining operation of the amplifier device.

Abstract: A monolithically integrated capacitor having a variable capacitance, comprising a first semiconductor region structure doped to a first doping type, a second semiconductor region structure doped to a second doping type opposite the first doping type, a first electrode of the capacitor connected to the semiconductor region structure, and a second electrode of the capacitor connected to the second semiconductor region structure. The second semiconductor region structure is located in contact with, and laterally arranged at least on two opposite sides of, the first semiconductor region structure, and a boundary, preferably a planar boundary, between the first and second semiconductor region structures is angled with respect to a plane having a laterally directed normal. Preferably, the second semiconductor region structure is partly or completely surrounding the first semiconductor region structure in a lateral plane.

Abstract: An integrated capacitor having a variable capacitance and being formed in an SOI substrate, has a first region lightly doped to a first doping type, a second region doped to a second doping type opposite to the first doping type, and located at a first side of the first region, a third region doped to the first doping type and located at a second side of the first region, which is opposite to the first side, an insulating region on top of the first region, and a fourth doped region located on top of the insulating region. The second and fourth doped regions are connected to a first electrode, and the third region is connected to a second electrode. The fourth doped region is laterally separated from the third region by a distance to increase the range of the variable capacitance.

Abstract: A differential transistor pair comprises a plurality of transistor cells in a substrate. Each cell comprises first drain regions at the respective edge of the cell, and a second drain region in between. Source regions are located between the respective first drain region and the second drain region. First gate regions are located between the respective first drain region and the source regions, and second gate regions are located between the source regions and the second drain region. The first drain regions of all cells are interconnected to a common first drain terminal, and the second drain region of all cells are interconnected to a common second drain terminal. The first gate regions of all cells are interconnected to a common first gate terminal, and the second gate regions of all cells are interconnected to a common second gate terminal.

Abstract: A monolithically integrated bipolar transistor has an SOI substrate, a collector region in the SOI substrate, a base layer region on top of and in contact with the collector region, and an emitter layer region on top of and in contact with the base layer region, wherein the collector, base layer, and emitter layer regions are provided with separate contact regions. Further, a region of an insulating material, preferably an oxide or nitride, is provided in the base layer region, in the emitter layer region, or between the base and emitter layer regions, wherein the insulating region extends laterally at a fraction of a width of the base and emitter layer regions to reduce an effective width of the bipolar transistor to thereby eliminate any base push out effects that would otherwise occur.

Abstract: An integrated LDMOS transistor comprises a semiconductor substrate (11), an LDMOS gate region (17), LDMOS source (14) and drain (15) regions, and a channel region (13) arranged beneath the LDMOS gate region, where the channel region interconnects the LDMOS source and drain regions. The LDMOS gate region comprises first (18a) and second (18b) gate insulation layer regions, a centrally located gate-dividing insulation region (19) provided between the first and second gate insulation layer regions, and first (20a) and second (20b) individual gate conducting layer regions, each being provided on top of a respective one of the first and second gate insulation layer regions, and each being an etched outside spacer region at the centrally located insulation layer region.

Abstract: At the surface of a substrate a gate oxide layer is produced and is given a dual thickness. A first oxide layer is produced over the surface of a substrate by thermal oxidation and is covered by a mask layer defining suitably located openings. A material accelerating or retarding the oxidation of the substrate is ion implanted through the first oxide layer in the openings, after which the mask is removed and the thermal oxidation is continued over the now exposed total surface of the first oxide layer. The material used for ion implanting can be an oxidation rate promoting material such as chloride and bromine. The manufacturing method is simple and adds little to presently used process flows for fabricating MOS devices. The dual thickness of the gate oxide gives the manufactured MOS device a low level of total noise generated when using the device for instance in RF-circuits.

Abstract: An electromagnetic device in an integrated circuit, particularly an integrated circuit for radio frequency applications, comprises a MOS transistor structure (11; 11?) and a spiral inductor (12; 12, 41). The MOS transistor structure and the spiral inductor are arranged on top of each other to obtain an operative coupling between a MOS current (17; 23a-b) of the MOS transistor structure and a magnetic field (16) of the spiral inductor via the Hall effect, and an electric input (14, 15) is provided for controlling an electric quantity of either one of the MOS transistor structure and the spiral inductor in order to influence the operation of the other one of the MOS transistor structure and the spiral inductor via the operative coupling. The device may be used in a large variety of applications for obtaining various functions. A method of operating the electromagnetic device is also disclosed.

Abstract: An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2?; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath the LDMOS gate region, the channel interconnecting the LDMOS source and drain regions and having a laterally graded doping concentration. In order to obtain a lower parasitic capacitance coupling from the gate semiconductor region, the gate semiconductor layer region is provided with a laterally graded net doping concentration (P+N+; N+N?). A method for fabrication of the inventive LDMOS transistor device is further disclosed.

Abstract: A differential transistor pair comprises a plurality of transistor cells in a substrate. Each cell comprises first drain regions at the respective edge of the cell, and a second drain region in between. Source regions are located between the respective first drain region and the second drain region. First gate regions are located between the respective first drain region and the source regions, and second gate regions are located between the source regions and the second drain region. The first drain regions of all cells are interconnected to a common first drain terminal, and the second drain region of all cells are interconnected to a common second drain terminal. The first gate regions of all cells are interconnected to a common first gate terminal, and the second gate regions of all cells are interconnected to a common second gate terminal.

Abstract: At the surface of a substrate a gate oxide layer is produced and is given a dual thickness. A first oxide layer is produced over the surface of a substrate by thermal oxidation and is covered by a mask layer defining suitably located openings. A material accelerating or retarding the oxidation of the substrate is ion implanted through the first oxide layer in the openings, after which the mask is removed and the thermal oxidation is continued over the now exposed total surface of the first oxide layer. The material used for ion implanting can be an oxidation rate promoting material such as chloride and bromine. The manufacturing method is simple and adds little to presently used process flows for fabricating MOS devices. The dual thickness of the gate oxide gives the manufactured MOS device a low level of total noise generated when using the device for instance in RF-circuits.

Abstract: A mixer includes a first terminal and a second terminal forming a first input port for receiving a first signal having a first frequency; a second input port for receiving a second signal having a second frequency; a mixer output port for a resulting signal; a first group of valves having their control inputs coupled to the first terminal for receiving the first signal; a second group of valves having their control inputs coupled to the second terminal for receiving the first signal; and a third group of two valves having their control inputs coupled for receiving the second signal. The valves co-operate such that in operation the mixer produces the resulting signal responsive to the first and second signals. The mixer also includes at least one passive low pass filter having an inductor, the low pass filter being connected to the control input of a valve in the first and second groups.

Abstract: In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The method includes providing a semiconductor substrate (1) with an n-doped collector layer (5) surrounded by isolation areas (4), implanting antimony ions into the collector layer such that a thin highly n-doped layer (18) is formed in the uppermost portion of the collector layer, and forming a base on top of said thin highly n-doped layer (18).

Abstract: A mixer includes a first terminal and a second terminal forming a first input port for receiving a first signal having a first frequency; a second input port for receiving a second signal having a second frequency; a mixer output port for a resulting signal; a first group of valves having their control inputs coupled to the first terminal for receiving the first signal; a second group of valves having their control inputs coupled to the second terminal for receiving the first signal; and a third group of two valves having their control inputs coupled for receiving the second signal. The valves co-operate such that in operation the mixer produces the resulting signal responsive to the first and second signals. The mixer also includes at least one passive low pass filter having an inductor, the low pass filter being connected to the control input of a valve in the first and second groups.

Abstract: In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics, comprising the steps of:

Abstract: The present disclosure describes a method to reduce the base-collector capacitance swing and increase the collector-to-base breakdown voltage in a bipolar high-frequency transistor. First a highly doped silicon substrate (1) of a first doping is selected for forming a transistor emitter region. Then layers (5, and 6, 7) are deposited with a second and a first doping for forming a base/collector structure. Subsequently a collector mesa structure is formed by removing silicon on base contact areas using a photoresist mask on top of a layer of for instance an oxide (9) so that the additional layers also serve as a mask for the silicon etch. An etching method is selected to facilitate the form of the collector to be made narrow closer to a collector contact surface, thereby creating a bipolar collector-up high frequency transistor with a shaped collector. This improves both the capacitance swing and the breakdown voltage.

Abstract: A bipolar power transistor intended for radio frequency applications, especially for use in an amplifier stage in a radio base station, and a method for manufacturing the bipolar power transistor are provided. The power transistor includes a substrate (13), an epitaxial collector layer (15) on the substrate (13), a base (19) and an emitter (21) formed in the collector layer (15). The degree of doping Nc(x) of the collector layer varies from its upper surface (24) and downwards to at least half the depth of the collector layer, essentially according to a polynom of at least the second degree, a0+a1x+a2x2+ . . . , where a0 is the degree of doping at the upper surface (24), x is the vertical distance from the same surface (24) and a1, a2, . . . are constants. The transistor can further include an at least approximately 2&mgr; thick insulation oxide (17) between the epitaxial collector layer (15) and higher situated metallic connections layers (31, 33).