Patents by Inventor Torsten Hinz
Torsten Hinz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8917875Abstract: A circuit for operating loudspeakers includes a first, second, third and fourth loudspeaker circuit, having one input each for injecting a signal and one output each for connecting a loudspeaker input. The loudspeaker circuits are designed to amplify the injected signal and to provide the amplified signal at the outputs thereof. The loudspeaker circuits can, for example, be used for a 2.1 sound system. The three channels for a 2.1 sound system can be implemented by an amplifier circuit with four loudspeaker circuits, one loudspeaker circuit each being required for the two stereo channels left and right. A subwoofer channel can be driven differentially by two loudspeaker circuits. The stereo channels are, by contrast, only still connected to one loudspeaker circuit each, and so the stereo channels require at least one further common ground cable.Type: GrantFiled: September 29, 2011Date of Patent: December 23, 2014Assignee: Infineon Technologies AGInventors: Christoph Braun, Thomas Duda, Torsten Hinz
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Patent number: 8904083Abstract: A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory.Type: GrantFiled: July 30, 2008Date of Patent: December 2, 2014Assignee: Infineon Technologies AGInventor: Torsten Hinz
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Publication number: 20140281086Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Inventors: Tommaso Bacigalupo, Torsten Hinz
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Patent number: 8410963Abstract: In an embodiment, an oversampled data converter includes a lowpass filter having a filter stage comprising a dynamic limiter, where the dynamic limiter having a limit set by an signal level at an input to the oversampled data converter. The oversampled data converter also includes a quantizing block comprising an input coupled to an output of the lowpass filter and an output coupled to an input of the lowpass filter.Type: GrantFiled: March 23, 2011Date of Patent: April 2, 2013Assignee: Infineon Technologies AGInventor: Torsten Hinz
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Patent number: 8321652Abstract: An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with pointers to locations of the memory management blocks. A volatile memory device is included with an address index table formed with pointers to the pointers to the locations of the memory management blocks. The address index table is stored in the nonvolatile memory upon loss of bias voltage. Changes to the address translation table are accumulated in the volatile memory and written to the address translation table when at least a minimum quantity of the changes has been accumulated. The changes to the logical block address translation table accumulated in the volatile memory are written to a page in the address translation table after prior data in the page has been updated, written to another page, and then erased.Type: GrantFiled: August 1, 2008Date of Patent: November 27, 2012Assignee: Infineon Technologies AGInventor: Torsten Hinz
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Publication number: 20120242522Abstract: In an embodiment, an oversampled data converter includes a lowpass filter having a filter stage comprising a dynamic limiter, where the dynamic limiter having a limit set by an signal level at an input to the oversampled data converter. The oversampled data converter also includes a quantizing block comprising an input coupled to an output of the lowpass filter and an output coupled to an input of the lowpass filter.Type: ApplicationFiled: March 23, 2011Publication date: September 27, 2012Inventor: Torsten Hinz
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Patent number: 8250436Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.Type: GrantFiled: November 2, 2011Date of Patent: August 21, 2012Assignee: Qimonda AGInventors: Torsten Hinz, Gerhard Risse
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Publication number: 20120140930Abstract: A circuit for operating loudspeakers includes a first, second, third and fourth loudspeaker circuit, having one input each for injecting a signal and one output each for connecting a loudspeaker input. The loudspeaker circuits are designed to amplify the injected signal and to provide the amplified signal at the outputs thereof. The loudspeaker circuits can, for example, be used for a 2.1 sound system. The three channels for a 2.1 sound system can be implemented by an amplifier circuit with four loudspeaker circuits, one loudspeaker circuit each being required for the two stereo channels left and right. A subwoofer channel can be driven differentially by two loudspeaker circuits. The stereo channels are, by contrast, only still connected to one loudspeaker circuit each, and so the stereo channels require at least one further common ground cable.Type: ApplicationFiled: September 29, 2011Publication date: June 7, 2012Applicant: Infeneon Technologies AGInventors: Christoph Braun, Thomas Duda, Torsten Hinz
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Publication number: 20120110414Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.Type: ApplicationFiled: November 2, 2011Publication date: May 3, 2012Applicant: QIMONDA AGInventors: Torsten Hinz, Gerhard Risse
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Patent number: 8078937Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.Type: GrantFiled: April 26, 2007Date of Patent: December 13, 2011Assignee: Qimonda AGInventors: Torsten Hinz, Gerhard Risse
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Patent number: 8046530Abstract: An embodiment of the invention relates to a nonvolatile mass storage device such as a flash memory device formed with erase blocks partitioned into memory management blocks. An erase block is identified containing at least a minimum number of management blocks marked invalid, from which data is copied, merged, and stored in a new management block. The erase block is then erased. Erase blocks containing at least the minimum number of invalid management blocks may be erased until a minimum amount of management blocks is free. Alternatively, all erase blocks containing at least the minimum number of invalid management blocks may be erased. A management table listing the number of invalid management blocks in erase blocks may be included in the mass storage device. Preferably, the new management block for storage of the merged data is located in an erase block different from the identified erase block.Type: GrantFiled: October 2, 2008Date of Patent: October 25, 2011Assignee: Infineon Technologies AGInventor: Torsten Hinz
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Patent number: 7888975Abstract: The invention relates to a line driver to drive a transmission line with a differentially balanced signal, with selectable signal amplitude, with output impedance matched to a characteristic impedance of the transmission line, and with reduced dissipation. The line driver includes a first driver subcircuit including a first and a second group of resistors. To drive an output node with a first signal sense, the first group of resistors is selectively coupled to a first bias voltage terminal and the second group to a second bias voltage terminal. To drive the first output node with a second signal sense, the first and second groups of resistors are both selectively coupled to the second bias voltage terminal. The line driver includes a second driver subcircuit. The second driver subcircuit includes a third and fourth group of resistors that are correspondingly switched.Type: GrantFiled: April 23, 2008Date of Patent: February 15, 2011Assignee: Infineon Technologies AGInventors: Torsten Hinz, Daniele Gardellini
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Publication number: 20100088482Abstract: An embodiment of the invention relates to a nonvolatile mass storage device such as a flash memory device formed with erase blocks partitioned into memory management blocks. An erase block is identified containing at least a minimum number of management blocks marked invalid, from which data is copied, merged, and stored in a new management block. The erase block is then erased. Erase blocks containing at least the minimum number of invalid management blocks may be erased until a minimum amount of management blocks is free. Alternatively, all erase blocks containing at least the minimum number of invalid management blocks may be erased. A management table listing the number of invalid management blocks in erase blocks may be included in the mass storage device. Preferably, the new management block for storage of the merged data is located in an erase block different from the identified erase block.Type: ApplicationFiled: October 2, 2008Publication date: April 8, 2010Inventor: Torsten Hinz
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Publication number: 20100030944Abstract: A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory.Type: ApplicationFiled: July 30, 2008Publication date: February 4, 2010Inventor: Torsten Hinz
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Publication number: 20100030999Abstract: An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with pointers to locations of the memory management blocks. A volatile memory device is included with an address index table formed with pointers to the pointers to the locations of the memory management blocks. The address index table is stored in the nonvolatile memory upon loss of bias voltage. Changes to the address translation table are accumulated in the volatile memory and written to the address translation table when at least a minimum quantity of the changes has been accumulated. The changes to the logical block address translation table accumulated in the volatile memory are written to a page in the address translation table after prior data in the page has been updated, written to another page, and then erased.Type: ApplicationFiled: August 1, 2008Publication date: February 4, 2010Inventor: Torsten Hinz
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Publication number: 20090267654Abstract: The invention relates to a line driver to drive a transmission line with a differentially balanced signal, with selectable signal amplitude, with output impedance matched to a characteristic impedance of the transmission line, and with reduced dissipation. The line driver includes a first driver subcircuit including a first and a second group of resistors. To drive an output node with a first signal sense, the first group of resistors is selectively coupled to a first bias voltage terminal and the second group to a second bias voltage terminal. To drive the first output node with a second signal sense, the first and second groups of resistors are both selectively coupled to the second bias voltage terminal. The line driver includes a second driver subcircuit. The second driver subcircuit includes a third and fourth group of resistors that are correspondingly switched.Type: ApplicationFiled: April 23, 2008Publication date: October 29, 2009Inventors: Torsten Hinz, Daniele Gardellini
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Publication number: 20090040082Abstract: A device for processing binary data comprises at least one transmission link having an input for receiving a serial bit stream and an output for forwarding bits in a parallel format, and a serial/parallel converter providing n?2 successive data bits of the serial bit stream as n-bit data words in the parallel format.Type: ApplicationFiled: July 24, 2008Publication date: February 12, 2009Inventors: Torsten Hinz, Otto Schumacher, Patrick Runkel, Russell Homer
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Publication number: 20090037764Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.Type: ApplicationFiled: April 26, 2007Publication date: February 5, 2009Applicant: Qimonda AGInventors: Torsten Hinz, Gerhard Risse
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Patent number: 7456665Abstract: A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.Type: GrantFiled: August 16, 2006Date of Patent: November 25, 2008Assignee: Qimonda AGInventors: Torsten Hinz, Andreas Jakobs, Benaissa Zaryouh
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Patent number: 7349508Abstract: A method and a device for reconstructing data, clocked at a symbol rate, from a signal which has been distorted by transmission of a transmission link, are disclosed. The method or respectively, the device, being predominantly performed or implemented, respectively, by means of digital circuit technology in order to improve the quality of the data recovery. The method includes amplifying the signal amplitude attenuated by the transmission; filtering high-frequency interference frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter; performing a cable approximation by means of a digitally implemented cable approximation filter in order to obtain an equalized signal; and recovering the data from the equalized signal by means of a phase-locked loop.Type: GrantFiled: November 14, 2003Date of Patent: March 25, 2008Assignee: Infineon Technologies AGInventors: Thomas Duda, Lajos Gaszi, Peter Gregorius, Torsten Hinz, Martin Renner