Abstract: The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

Abstract: A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

Abstract: The invention provides a method for recovering a digital datastream, in which a reference clock phase is recovered from the digital datastream, the digital datastream being received in a datastream receiver, low-pass filtered in a low-pass filter device, an edge position signal being determined by comparing an amplitude of the low-pass filtered datastream with a predetermined threshold value in an edge position detection device and a phase deviation being determined from a time difference between a 0/1 threshold intersection point of the threshold value with a 0/1 data transition or a ?1/1 threshold intersection point of the threshold value with a ?1/1 data transmission and the target time of the control system in a phase correction device, so that the phase deviation can be corrected with the phase correction offset in the phase correction device.

Abstract: The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

Abstract: In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal (RX), having a clock-signal recovery unit (3) for recovering a clock signal belonging to the transmitted data from the received data signal, and having a data reconstruction unit (2) for reconstructing the transmitted data from the received data signal using the recovered clock signal (fCLK), and for emitting a data stream (DATA) which is synchronised with the recovered clock signal.

Abstract: A digitally controlled circuit for reducing the phase modulation of a signal. The circuit has a multiphase clock generator that produces n phases of a clock that is m-times the signal. The circuit further has a multiplexer with n inputs for the n phases of the clock and with one output which supplies the output signal. The output signal and the signal are connected to the inputs of a phase comparator. The output signal of the comparator is supplied to a sigma-delta modulator whose output signals are used for controlling the multiplexer. A jittered input signal is compared in the phase comparator with a master clock. The determined phase difference is integrated in a sigma-delta modulator. The aim of the circuit is to generate a clock without jitter, digitally and without using external components. This circuit provides 20 dB/decade attenuation of the jitter received in the SYNC signal, based on the P-regulator characteristic.

Abstract: In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal (RX), having a clock-signal recovery unit (3) for recovering a clock signal belonging to the transmitted data from the received data signal, and having a data reconstruction unit (2) for reconstructing the transmitted data from the received data signal using the recovered clock signal (fCLK), and for emitting a data stream (DATA) which is synchronised with the recovered clock signal.

Abstract: The invention provides a method for recovering a digital datastream (301), in which a reference clock phase (308) is recovered from the digital datastream (301), the digital datastream (301) being received in a datastream receiver (302), low-pass filtered in a low-pass filter device (303), an edge position signal (309) being determined by comparing an amplitude of the low-pass filtered datastream (305) with a predeterminable threshold value (108) in an edge position detection device (304) and a phase deviation (111a) being determined from a time difference between a 0/1 threshold intersection point (109) of the threshold value (108) with a 0/1 data transition (101) or a −1/1 threshold intersection point (110) of the threshold value (108) with a −1/1 data transmission (102) and the target time of the control system (310) in a phase correction device (307), so that the phase deviation (111a) can be corrected with the phase correction offset (111b) in the phase correction device (307).

Abstract: A method and a device for reconstructing data, clocked at a symbol rate, from a signal which has been distorted by transmission of a transmission link, are disclosed. The method or respectively, the device, being predominantly performed or implemented, respectively, by means of digital circuit technology in order to improve the quality of the data recovery. The method comprises amplifying the signal amplitude attenuated by the transmission; filtering high-frequency interference frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter (3); performing a cable approximation by means of a digitally implemented cable approximation filter (7) in order to obtain an equalized signal; and recovering the data from the equalized signal by means of a phase-locked loop (20).