Abstract: A substrate processing apparatus includes a substrate holding unit that horizontally holds a substrate in non-contact with a major surface of the substrate, a processing liquid supply unit that supplies a processing liquid to the major surface of the substrate held by the substrate holding unit, and a hydrophilic surface placing unit that places an annular hydrophilic surface along a peripheral portion of the major surface of the substrate held by the substrate holding unit such that the hydrophilic surface comes into contact with a liquid film of the processing liquid held on the major surface of the substrate.

Abstract: An IC label for prevention of forgery includes: a label substrate which has an adhesive agent for affixing the same to an object; a non-contact IC medium which is provided on the label substrate and has an IC chip for storing predetermined identification information and an antenna for wireless transmission of the identification information; and a security function portion which is provided on the label substrate and prevents replication.

Abstract: A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

Abstract: A semiconductor memory device includes a first reference circuit which generates a first reference potential, a second reference circuit which generates a second reference potential, a memory cell, a first sense amplifier which senses a data potential read from the memory cell through comparison with the first reference potential, and a second sense amplifier which senses the data potential read from the memory cell through comparison with the second reference potential, wherein the first sense amplifier and the second sense amplifier cooperate to determine whether the data potential is “0” or “1”, the first reference potential being positioned on a highest potential side of a data potential distribution of a “0” data potential read from the memory cell, and the second reference potential being positioned on a lowest potential side of a data potential distribution of a “1” data potential read from the memory cell.

Abstract: A semiconductor memory device includes a first reference circuit which generates a first reference potential, a second reference circuit which generates a second reference potential, a memory cell, a first sense amplifier which senses a data potential read from the memory cell through comparison with the first reference potential, and a second sense amplifier which senses the data potential read from the memory cell through comparison with the second reference potential, wherein the first sense amplifier and the second sense amplifier cooperate to determine whether the data potential is “0” or “1”, the first reference potential being positioned on a highest potential side of a data potential distribution of a “0” data potential read from the memory cell, and the second reference potential being positioned on a lowest potential side of a data potential distribution of a “1” data potential read from the memory cell.

Abstract: A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

Abstract: An output node NO is, on one hand, connected through a PMOS transistor TP1 and an NMOS transistor TN1 to ground, and on the other hand, connected through a PMOS transistor TP2 and an NMOS transistor TN2 to a node N6 which is selectively set to ground and VDD. The output node NO is connected through a capacitor C1 to the input of a driving inverter 11 in order to step-up or step-down the voltage of the output node NO. When the output node NO is set to −1V, the control circuit 10 turns off the PMOS transistors TP1 and TP2. It is also allowed to connect the output node through a first PMOS transistor to a second PMOS transistor whose back gate is connected to a power supply voltage VDD, and to connect the back gate of the first PMOS transistor to one end of a current path thereof on the side of the second PMOS transistor.

Abstract: An output node NO is, on one hand, connected through a PMOS transistor TP1 and an NMOS transistor TN1 to ground, and on the other hand, connected through a PMOS transistor TP2 and an NMOS transistor TN2 to a node N6 which is selectively set to ground and VDD. The output node NO is connected through a capacitor C1 to the input of a driving inverter 11 in order to step-up or step-down the voltage of the output node NO. When the output node NO is set to −1V, the control circuit 10 turns off the PMOS transistors TP1 and TP2. It is also allowed to connect the output node through a first PMOS transistor to a second PMOS transistor whose back gate is connected to a power supply voltage VDD, and to connect the back gate of the first PMOS transistor to one end of a current path thereof on the side of the second PMOS transistor.

Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.

Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.

Abstract: A lease-business support apparatus collects latest information from a brand-new-sales-company terminal, a secondhand-sales-company terminal, a leasing-company terminal, and a maintenance-company terminal which are related to lease business. By performing quality management and appropriate fixed-period-sales-price calculation based on the latest information, the lease-business support apparatus provides each customer terminal with appropriate lease-business information. This makes it possible to inexpensively lease a high-quality item.

Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.

Abstract: The present invention provides a non-volatile memory circuit that can easily read and write. Especially, the present invention is effective to storage multi-value or analog value. The present invention has a storage transistor Nc with a floating gate and a feedback transistor Nf with a floating gate whose source are connected commonly and a load circuit is provided to the drain side of both transistors. A negative feedback circuit is provided between the drain of the storage transistor Nc and the floating gate of the feedback transistor Nf. An output transistor P2 is a preferable example of the negative feedback circuit, whose gate is connected to the drain of the storage transistor and which generates a voltage corresponding to that gate voltage at an output terminal. This output terminal and the floating gate of the feedback transistor are connected.

Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.

Abstract: A semiconductor device with a fuse is formed on a semiconductor substrate having a base semiconductor substrate and an epitaxial semiconductor layer formed thereon and defining a major surface of the semiconductor substrate. An isolation region is formed in the epitaxial semiconductor so as to completely surround and electrically isolate a selected region of the epitaxial layer on which the narrow, blowable portion of the fuse is disposed. A field oxide layer and an insulating layer are formed, in turn, over the fuse and on the main surface of the semiconductor layer and a passivation layer is formed on the insulating layer having an opening therein defined by interior sidewalls of the passivation layer which surround the selected region and which are disposed interiorally of the isolation region, and through which first opening a corresponding service of the insulating layer is exposed.

Abstract: A semiconductor integrated circuit includes an input circuit having a CMOS inverter and receiving an input signal. The input circuit has a threshold level which determines an output level of the input circuit with respect to the input signal. The integrated circuit includes an internal circuit receiving the input signal via the input circuit, the internal circuit receiving a first power supply voltage. A power source generates a second power supply voltage applied to the input circuit so that the second power supply voltage changes to cancel a change in the threshold level due to a temperature variation.