Patents by Inventor Toru Koga

Toru Koga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070082771
    Abstract: When a line pressure PL serving as a source pressure of a primary pulley (2) and a secondary pulley (3) is controlled on the basis of a control deviation ?Step, which is the deviation between a step count StepMdl of a step motor (27) corresponding to a target speed ratio I (o) and a value obtained by adding a target deviation GTstep and a starting learned value Gstep to a step count Bstep of the step motor (27) corresponding to an actual speed ratio ip, the engine torque varies dramatically beyond the range of a predetermined value T1 and a predetermined value T2 during a predetermined time period t1, a learning error determination relating to the starting learned value Gstep is prohibited for a predetermined time period t2.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 12, 2007
    Inventors: Tetsuya Izumi, Hironori Nihei, Seonjae Kim, Takeshi Chibahara, Toru Koga
  • Patent number: 7079443
    Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 18, 2006
    Assignee: Fujitsu Limited
    Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
  • Publication number: 20060098523
    Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.
    Type: Application
    Filed: December 22, 2005
    Publication date: May 11, 2006
    Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
  • Patent number: 7032142
    Abstract: A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: April 18, 2006
    Assignee: Fujitsu Limited
    Inventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara, Toru Koga, Katsuhiro Mori
  • Patent number: 6845055
    Abstract: A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: January 18, 2005
    Assignee: Fujitsu Limited
    Inventors: Toru Koga, Tomohiro Kawakubo, Tatsuya Kanda
  • Patent number: 6831870
    Abstract: Main memory units are each composed of an even number of sub memory units having different addresses. The sub memory units have memory cells, bit lines corresponding to different data terminals with numbers, sense amplifiers, and column switch circuits for connecting the bit lines to data bus lines. Column switch areas of the main memory units are formed in mirror symmetry. Consequently, the sequence of the data terminal numbers of the bit lines in the case of relief where a redundancy memory unit is used can be easily made the same as in the case of non-relief where the redundancy memory unit is not used. As a result, at the time of defect analysis, the sequence of the bit lines need not be taken into account regardless of whether the product is a relief product or non-relief product. This allows a reduction in the time necessary for defect analysis.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: December 14, 2004
    Assignee: Fujitsu Limited
    Inventor: Toru Koga
  • Publication number: 20040114442
    Abstract: Main memory units are each composed of an even number of sub memory units having different addresses. The sub memory units have memory cells, bit lines corresponding to different data terminals with numbers, sense amplifiers, and column switch circuits for connecting the bit lines to data bus lines. Column switch areas of the main memory units are formed in mirror symmetry. Consequently, the sequence of the data terminal numbers of the bit lines in the case of relief where a redundancy memory unit is used can be easily made the same as in the case of non-relief where the redundancy memory unit is not used. As a result, at the time of defect analysis, the sequence of the bit lines need not be taken into account regardless of whether the product is a relief product or non-relief product. This allows a reduction in the time necessary for defect analysis.
    Type: Application
    Filed: July 29, 2003
    Publication date: June 17, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Toru Koga
  • Publication number: 20040022091
    Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 5, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
  • Patent number: 6683491
    Abstract: First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: January 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Toru Koga, Shinya Fujioka, Katsuhiro Mori
  • Patent number: 6628564
    Abstract: A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: September 30, 2003
    Assignee: Fujitsu Limited
    Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
  • Patent number: 6605963
    Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: August 12, 2003
    Assignee: Fujitsu Limited
    Inventors: Ayako Kitamoto, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Hideki Kanou, Kuninori Kawabata, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Publication number: 20030106010
    Abstract: A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.
    Type: Application
    Filed: October 17, 2002
    Publication date: June 5, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara, Toru Koga, Katsuhiro Mori
  • Publication number: 20030098741
    Abstract: First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.
    Type: Application
    Filed: March 27, 2002
    Publication date: May 29, 2003
    Applicant: Fujitsu Limited
    Inventors: Toru Koga, Shinya Fujioka, Katsuhiro Mori
  • Patent number: 6538493
    Abstract: A first transistor is turned on during operation of a circuit block, to connect a substrate of the transistor to a first substrate voltage line. A second transistor is turned on during non-operation of the circuit block, to connect the substrate of the transistor to a second substrate voltage line. ON resistance of the second transistor is higher than that of the first transistor. A source-to-substrate voltage of the transistor being not in operation is set to be higher than that of the transistor being in operation. When a semiconductor integrated circuit switches from the operation state to the non-operation state, its substrate voltage changes gradually to a second substrate voltage. Charging/discharging currents of the substrate voltage can be dispersed so that it is possible to suppress current consumption in shifting from the operation state to the non-operation state and reduce a standby current in the non-operation state.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: March 25, 2003
    Assignee: Fujitsu Limited
    Inventors: Toru Koga, Shinichi Yamada, Masato Takita
  • Publication number: 20030006833
    Abstract: A first transistor is turned on during operation of a circuit block, to connect a substrate of the transistor to a first substrate voltage line. A second transistor is turned on during non-operation of the circuit block, to connect the substrate of the transistor to a second substrate voltage line. ON resistance of the second transistor is higher than that of the first transistor. A source-to-substrate voltage of the transistor being not in operation is set to be higher than that of the transistor being in operation. When a semiconductor integrated circuit switches from the operation state to the non-operation state, its substrate voltage changes gradually to a second substrate voltage. Charging/discharging currents of the substrate voltage can be dispersed so that it is possible to suppress current consumption in shifting from the operation state to the non-operation state and reduce a standby current in the non-operation state.
    Type: Application
    Filed: December 19, 2001
    Publication date: January 9, 2003
    Applicant: Fujitsu Limited
    Inventors: Toru Koga, Shinichi Yamada, Masato Takita
  • Publication number: 20020145447
    Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.
    Type: Application
    Filed: October 5, 1999
    Publication date: October 10, 2002
    Inventors: AYAKO KITAMOTO, MASATO MATSUMIYA, SATOSHI ETO, MASATO TAKITA, TOSHIKAZU NAKAMURA, HIDEKI KANOU, KUNINORI KAWABATA, MASATOMO HASEGAWA, TORU KOGA, YUKI ISHII
  • Patent number: 6377101
    Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: April 23, 2002
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
  • Publication number: 20020021157
    Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
    Type: Application
    Filed: February 22, 2000
    Publication date: February 21, 2002
    Inventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
  • Patent number: 6252269
    Abstract: According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: June 26, 2001
    Assignee: Fujitsu Limited
    Inventors: Masatomo Hasegawa, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii
  • Patent number: 6229363
    Abstract: A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: May 8, 2001
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masato Matsumiya, Masato Takita, Toshikazu Nakamura, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Masatomo Hasegawa, Toru Koga, Yuki Ishii