Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a first and second stacked portions including first and second conductive layers and having first and second end portions stepwise processed, a first and second interlayer insulating layers covering the first and second end portions, a first stopper insulating layer provided at least between the first and second interlayer insulating layers and above the first end portion, including a first portion extending flat above the first end portion, and first contacts penetrating the second interlayer insulating layer, the first portion of the first stopper insulating layer and the first interlayer insulating layer, and connected to different first conductive layers.

Abstract: A first region includes a memory cell transistor. A second region is adjacent to the first region in a first direction, and includes first and second subregions aligned in a second direction. First members include a portion extending along the first direction, and are provided in the first subregion. The first members are arranged in such a manner that the first members aligned in the second direction in an n-th row and an (n+1)-th row, counted from a side of the second subregion, are shifted in the first direction. The first members adjacent to each other in the second direction are arranged in such a manner that portions extending in the first direction face each other.

Abstract: A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.

Abstract: A first region includes a memory cell transistor. A second region is adjacent to the first region in a first direction, and includes first and second subregions aligned in a second direction. First members include a portion extending along the first direction, and are provided in the first subregion. The first members are arranged in such a manner that the first members aligned in the second direction in an n-th row and an (n+1)-th row, counted from a side of the second subregion, are shifted in the first direction. The first members adjacent to each other in the second direction are arranged in such a manner that portions extending in the first direction face each other.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

Abstract: A method of controlling user information for an information processing apparatus includes the steps of a process of an application program requesting user information controlling unit to obtain an item of said user information, and said user information controlling unit providing the obtained item of said user information to said process. The user information controlling unit obtains the user information requested by the process of an application program and provides the user information to the process. Accordingly, the user information can be shared by the application programs and centrally controlled.

Abstract: An information processing apparatus that includes a plurality of communicating units, and that is capable of performing at least one function, includes an identifying unit and a processing unit. The identifying unit identifies the communicating unit connected to an external device. The processing unit performs processing corresponding to the communicating unit identified by the identifying unit, by using correspondence information that indicates correspondence between the communicating unit and regulation information.

Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A semiconductor memory device includes electrode layers stacked on a conductive layer, and columnar bodies extending in the electrode layers in a stacked direction of the electrode layers. The electrode layers include a first electrode layer and a second electrode layer positioned between the first electrode layer and the conductive layer. The columnar bodies include a first columnar body and a second columnar body. The first columnar body includes a first semiconductor layer extending in the stacked direction through the first electrode, a semiconductor body provided between the first semiconductor layer and the conductive layer, and a first insulating layer extending along the first semiconductor layer. The second columnar body includes a second semiconductor layer extending in the stacked direction through at least the first electrode layer, and a second insulating layer extending in the stacked direction along the second semiconductor layer and extending through the second electrode layer.

Abstract: According to an embodiment, a semiconductor memory device comprises a first region, a second region, and a third region. The first region includes: a part of a stacked body that includes a plurality of conductive layers; and a memory columnar body which has its side surface covered by the stacked body and configures a memory string. The second region includes: a contact; a contact portion connected to the contact, of the conductive layer; and a plurality of first columnar bodies. The third region includes a second columnar body. In a plane parallel to the substrate, a total area of the second columnar body in a small region that has the same area as one or more contact portions, in the third region is larger than a total area of the first columnar body in the one or more contact portions.

Abstract: According to an embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film, a first structure body, and a first connection portion. The stacked body includes a first conductive layer and a second conductive layer. The semiconductor pillar extends in the first direction through the stacked body. The memory film provides between the stacked body and the semiconductor pillar. The first conductive layer includes a first region and a second region. The first region does not overlap the second conductive layer in the first direction. The second region overlaps the second conductive layer in the first direction. The first structure body extends in the first direction through the first region to a position of a front surface of the first region. The first connection portion is electrically connected to the first conductive layer.

Abstract: According to an embodiment, a semiconductor memory device comprises a first region, a second region, and a third region. The first region includes: a part of a stacked body that includes a plurality of conductive layers; and a memory columnar body which has its side surface covered by the stacked body and configures a memory string. The second region includes: a contact; a contact portion connected to the contact, of the conductive layer; and a plurality of first columnar bodies. The third region includes a second columnar body. In a plane parallel to the substrate, a total area of the second columnar body in a small region that has the same area as one or more contact portions, in the third region is larger than a total area of the first columnar body in the one or more contact portions.