SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF
A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
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This application is a continuation of U.S. application Ser. No. 14/849,743, filed Sep. 10, 2015, which is based upon and claims the benefit of priority from U.S. Provisional Application 62/132,886, filed on Mar. 13, 2015, the entire contents of each which are incorporated herein by reference.
BACKGROUND FieldThe present invention relates to a semiconductor memory device and a production method thereof.
Description of the Related ArtAs one of semiconductor memory devices, a flash memory has been known. Particularly, a NAND-type flash memory has been widely used generally, because the NAND-type flash memory has a low cost and a high capacity. A large number of technologies for increasing a capacity of the NAND-type flash memory have been suggested. One of the technologies is a structure in which memory cells are arranged three-dimensionally.
A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting a plurality of first selection transistors, a plurality of memory transistors, and a plurality of second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has a plurality of first conductive layers to be control gates of the plurality of first selection transistors, a plurality of second conductive layers to be control gates of the plurality of memory transistors, and a plurality of third conductive layers to be control gates of the plurality of second selection transistors, which are laminated in the third direction. Ends of the plurality of first conductive layers and ends of the plurality of third conductive layers are formed in shapes of steps extending in the first direction and ends of the plurality of second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
Hereinafter, a semiconductor memory device and a production method thereof according to an embodiment of an embodiment will be described with reference to the drawings.
[Configuration of Semiconductor Memory Device According to Embodiment]First, an entire configuration of a semiconductor memory device according to an embodiment will be described.
The semiconductor memory device according to the embodiment includes a memory cell array 1, row decoders 2 and 3, a sense amplifier 4, a column decoder 5, and a control signal generating unit 6. The memory cell array 1 has a plurality of memory blocks MB. Each memory block MB has a plurality of memory transistors MT to be a plurality of memory cells MC arranged three-dimensionally and becomes a unit of an erasure operation of data. The individual memory blocks MB are divided by a plurality of grooves extending in one direction. Hereinafter, an area interposed between adjacent grooves is called a “finger”. The row decoders 2 and 3 decode a block address signal taken and control a write operation and a read operation of data of the memory cell array 1. The sense amplifier 4 detects an electric signal flowing to the memory cell array 1 at the time of the read operation and amplifies the electric signal. The column decoder 5 decodes a column address signal and controls the sense amplifier 4. The control signal generating unit 6 boosts a reference voltage to generate a high voltage used at the time of the write operation or an erasure operation and generates a control signal to control the row decoders 2 and 3, the sense amplifier 4, and the column decoder 5.
Next, the memory cell array 1 will be described.
As illustrated in
The memory cell array 1 has a plurality of memory columnar bodies 104 extending in the Z direction. A crossing part of the conductive layer 101 and the memory columnar body 104 functions as a source-side selection transistor STS. A crossing part of the conductive layer 102 and the memory columnar body 104 functions as the memory transistor MT. A crossing part of the conductive layer 103 and the memory columnar body 104 functions as a drain-side selection transistor STD. Hereinafter, the source-side selection transistor STS and the drain-side selection transistor STD are called “selection transistors”.
In addition, the plurality of conductive layers 101 to 103 have contact units 101a to 103a in which ends thereof are formed in shapes of steps, respectively. The contact units 101a to 103a have portions that do not face bottom surfaces of other contact units 101a to 103a positioned at upper layers. These portions are called “terraces” hereinafter.
Wiring lines of the conductive layers 101 to 103 have terraces at different positions in an X direction and a Y direction and vias 108 are connected to the terraces to prevent the vias 108 from interfering with each other. Wiring lines 109 are arranged on upper ends of the vias 108. The via 108 and the wiring line 109 are formed of tungsten (W).
In addition, the memory cell array 1 has a source contact LI that faces sides of the Y direction of the plurality of conductive layers 101 to 103 and extends in the X direction. A bottom surface of the source contact LI contacts the semiconductor substrate SB. The conductive layer 108 is formed of tungsten (W), for example.
In addition, the memory cell array 1 has a plurality of bit lines BL and a source line SL that are arranged on the conductive layers 101 to 103 and the memory columnar bodies 104 and extend in the X direction and the Y direction. The memory columnar body 104 is electrically connected to a bottom surface of each bit line BL. The bit line BL is formed of tungsten (W), for example. The source contact LI is electrically connected to a bottom surface of the source line SL. The source line SL is formed of tungsten (W), for example.
Hereinafter, in the memory cell array 1, an area in which the plurality of memory columnar bodies 104 are arranged is called a “memory area 106” and an area in which the contact units 101a to 103a of the plurality of conductive layers 101 to 103 are formed is called a “contact area 107”.
Next, the memory columnar body 104 and a peripheral structure thereof will be described.
The memory columnar body 104 has an oxide film core 111, a semiconductor film 112, a tunnel insulating film 113, a charge accumulation film 114, and a block insulating film 115, which are laminated outward from the center. The oxide film core 111 can be formed of a silicon oxide film (SiO2), for example. The semiconductor film 112 can be formed of silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), germanium (Ge), and carbon (C). The tunnel insulating film 113 and the block insulating film 115 can be formed of Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO, in addition to a silicon oxide film (SiOx). The charge accumulation film 114 can be formed of a silicon nitride film (SiN), for example. The tunnel insulating film 113 and the charge accumulation film 114 may be formed in a longitudinal direction of the memory columnar body 104 or may be formed at only positions of sides of the conductive layers 101 to 103.
By the structure described using
Next, an equivalent circuit of the memory unit MU will be described.
Each memory unit MU of the memory cell array 1 has a memory string MS including a plurality of memory transistors MT, a plurality of source-side selection transistors STS connected between a lower end of the memory string MS and the source line SL, and a plurality of drain-side selection transistors STD connected between an upper end of the memory string MS and the bit line BL. The source-side selection transistor STS, the memory transistor MT, and the drain-side selection transistor STD are connected in series from the source line SL to the bit line BL.
From the viewpoint of processing easiness of the memory cell array 1, it becomes advantageous to form the selection gate line SGS and SGD to have the small film thickness and the same film thickness as the film thickness of the word line WL. In this case, however, sufficient cutoff cannot be achieved by only one selection transistor. For this reason, in the memory unit MU according to the embodiment, the plurality of source-side selection transistors STS and the plurality of drain-side selection transistors STD are connected in series.
Hereinafter, structures of the contact units 101a to 103a according to the embodiment will be described. As the premise, structures of contact units according to two comparative examples will be described hereinafter.
Similar to the embodiment, the memory cell array according to the first comparative example has a plurality of conductive layers 201 becoming source-side selection gate lines SGS, a plurality of conductive layers 202 becoming word lines WL, and four conductive layers 203 becoming drain-side selection gate lines SGD, which are laminated from a lower layer to an upper layer. Ends of contact units 201a to 203a of the conductive layers 201 to 203 have stepwise structures extending in an X direction. In this case, because each of the conductive layers 201 to 203 can be divided into a plurality of parts (in the case of
Similar to the embodiment, a memory cell array (not illustrated in the drawings) according to a second comparative example has conductive layers 301 becoming source-side selection gate lines SGS, conductive layers 302 becoming word lines WL, and conductive layers 303 becoming drain-side selection gate lines SGD, which are laminated from a lower layer to an upper layer. However, different from the first comparative example, ends of contact units 301a to 303a of the conductive layers 301 to 303 have stepwise structures extending in both directions of an X direction and a Y direction. That is, a terrace of each wiring line is arranged in a checkerboard pattern, when viewed from the Z direction. In this case, because contact areas for the conductive layers 301 to 303 can be decreased, the chip size can be decreased as compared with the first comparative example. However, in the case of the second comparative example, because the contact units 301a to 303a cannot be divided into a plurality of parts, the selection gate lines SGS and SGD and the word line WL can be selected in only units of memory blocks MB. In this case, load to a memory string MS at the time of a read operation and a write operation becomes several times larger than load in the first comparison example.
Therefore, in this embodiment, the contact units 101a to 103a of the conductive layers 101 to 103 have the following structures.
As described above, in the memory cell array 1 according to the embodiment, the plurality of conductive layers 101 to 103 are laminated from the lower layer to the upper layer. In
Similar to the first comparative example, ends of the contact units 101a and 103a of the conductive layers 101 and 103 becoming the selection gate lines SGS and SGD have stepwise structures extending in the X direction. In each of the conductive layers 101 and 103, one or more vias 108 (in the case of
Meanwhile, the ends of the contact units 102a of the conductive layers 102 becoming the word lines WL have stepwise structures extending in both directions of the X direction and the Y direction, similar to the second comparative example. That is, a terrace of each wiring line is arranged in a checkerboard pattern, when viewed from the Z direction. In addition, the plurality of vias 108 (in the case of
In the cases of
As described above, in the case of the embodiment, the ends of the contact units 101a and 103a of the conductive layers 101 and 103 becoming the selection gate lines SGS and SGD are formed in the shapes of the steps extending in the X direction, so that the selection gate lines SGS and SGD can be selected for each finger, similar to the first comparative example. Thereby, load to the memory string MS at the time of the read operation and the write operation can be reduced as compared with the second comparative example. In addition, the ends of the contact units 102a of the conductive layers 102 becoming the word lines WL are formed in the shapes of the steps extending in both directions of the X direction and the Y direction, so that the width of the X direction of the contact area 107 can be decreased, as compared with the first comparative example.
As illustrated in
That is, according to the embodiment, a semiconductor memory device in which the chip size can be decreased as compared with the first comparative example and the load to the memory string MS at the time of the read operation and the write operation can be decreased as compared with the second comparative example can be provided.
[Method of Producing Semiconductor Memory Device According to Embodiment]Next, a process for producing the contact units 101a to 103a of the memory cell array 1 according to the embodiment will be described.
First, transistors configuring a peripheral circuit are formed on a silicon substrate 131.
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Next, after the silicon oxide film is formed on an interlayer insulating film 133 and the laminates 102′ and 103′, the silicon oxide film is flattened using the CMP. Next, formation of the memory transistor MT for the memory area 106 and formation of the via 108 for the contact area 107 are executed.
As such, the process for producing the contact units 101a to 103a is executed.
Next, another process for producing the contact units 101a to 103a of the memory cell array 1 according to the embodiment will be described.
First, transistors configuring a peripheral circuit are formed on the silicon substrate 131.
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Next, after the silicon oxide film is formed on the laminates 101′ to 103′, the silicon oxide film is flattened using the CMP. Next, formation of the memory transistor MT for the memory area 106 and formation of the via 108 for the contact area 107 are executed.
As such, another process for producing the contact units 101a to 103a is executed.
[Others]Some embodiments of the present invention have been described. However, the embodiments are only exemplary and do not limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms and various omissions, replacements, changes, and modifications can be made without departing from the gist of the invention. The embodiments and the modifications thereof are included in the scope and the gist of the invention and are included in the scope of the invention described in the claims.
Claims
1. A semiconductor memory device comprising:
- a memory cell array formed on a semiconductor substrate and configured to have a memory unit obtained by connecting a plurality of first selection transistors, a plurality of memory transistors, and a plurality of second selection transistors in series,
- when three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array having a plurality of first conductive layers to be control gates of the plurality of first selection transistors, a plurality of second conductive layers to be control gates of the plurality of memory transistors, and a plurality of third conductive layers to be control gates of the plurality of second selection transistors, which are laminated in the third direction,
- ends of the plurality of first conductive layers corresponding to control gates of the first selection transistors being formed such that at least one end of one first conductive layer extends farther in the first direction than a corresponding end of another first conductive layer disposed directly above the one first conductive layer,
- ends of the plurality of third conductive layers corresponding to control gates of the second selection transistors being formed such that at least one end of one third conductive layer extends farther in the first direction than a corresponding end of another third conductive layer disposed directly above the one third conductive layer,
- ends of the plurality of second conductive layers corresponding to control gates of the memory transistors being formed such that at least two ends of one second conductive layer extend farther respectively in the first direction and the second direction than corresponding ends of another second conductive layer disposed directly above the one second conductive layer, and
- the first direction and the second direction are parallel with the semiconductor substrate.
Type: Application
Filed: Nov 7, 2018
Publication Date: Mar 7, 2019
Applicant: Toshiba Memory Corporation (Minato-ku)
Inventors: Tadashi IGUCHI (Yokkaichi), Murato Kawai (Yokkaichi), Toru Matsuda (Yokkaichi), Hisashi Kato (Mie), Megumi Ishiduki (Yokkaichi)
Application Number: 16/183,389