Patents by Inventor Toru Onishi
Toru Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170092742Abstract: A method of manufacturing an insulated gate type switching device includes forming a gate trench that has a first portion with a first width in a first direction and a second portion with a second width in the first direction, the second width being wider than the first width. In an oblique implantation, second conductivity type impurities are irradiated at an irradiation angle inclined around an axis orthogonal to the first direction. The first width, the second width, and the irradiation angle are set such that the second conductivity type impurities are suppressed, at a first side surface of the first portion, from being. implanted into a part below a lower end of a second semiconductor region, and at a second side surface of the second portion, the impurities are implanted into the part below the lower end of the second semiconductor region.Type: ApplicationFiled: August 12, 2016Publication date: March 30, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru ONISHI, Atsushi ONOGI, Tadashi MISUMI, Yusuke YAMASHITA, Yuichi TAKEUCHI
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Patent number: 9608071Abstract: An IGBT manufacturing method is provided. The IGBT has an n-type emitter region, a p-type top body region, an n-type intermediate region, a p-type bottom body region, an n-type drift region, a p-type collector region, trenches penetrating the emitter region, the top body region, the intermediate region and the bottom body region from an upper surface of a semiconductor substrate and reaching the drift region, and gate electrodes formed in the trenches. The method includes forming the trenches on the upper surface of the semiconductor substrate, forming the insulating film in the trenches, forming an electrode layer on the semiconductor substrate and in the trenches after forming the insulating film, planarizing an upper surface of the electrode layer, and implanting n-type impurities to a depth of the intermediate region from the upper surface side of the semiconductor substrate after planarizing the upper surface of the electrode layer.Type: GrantFiled: February 14, 2012Date of Patent: March 28, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takehiro Kato, Toru Onishi
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Publication number: 20170033195Abstract: Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.Type: ApplicationFiled: February 25, 2015Publication date: February 2, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru ONISHI, Shuhei OKI, Tomoharu IKEDA, Rahman MD. TASBIR
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Publication number: 20160336402Abstract: A semiconductor device includes a plurality of trench gates provided abreast in a semiconductor substrate; an interlayer insulation film having opening from which a part of a front surface of the semiconductor substrate is exposed; and contact plugs provided in the openings. The interlayer insulation film comprises a plurality of first portions, each of which covers a corresponding one of the trench gates, and a plurality of second portions, each of which is provided between adjacent first portions and along a direction intersecting with the first portions. The openings are provided at an area surrounded by the first portions and the second portions, a length of the openings in a direction along the first portions is shorter than a length of the openings in a direction along the second portions intersecting with the first portions.Type: ApplicationFiled: November 12, 2014Publication date: November 17, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Toru ONISHI
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Patent number: 9443766Abstract: A diode manufacturing method provided herein includes first-third implantations and a heating. The first implantation implants n-type impurities into a first range at a first depth. The second implantation implants n-type impurities into a second range including the first range as a part at a second depth shallower than the first depth. The third implantation implants p-type impurities into a third range located on both sides of the second range at a third depth shallower than the first depth at a density higher than the second implantation. The semiconductor substrate is heated in the heating so that a first p-type region (contact region) is formed in the implanted region in the third implantation and a first n-type region (pillar region) is formed in a part of the implanted region in the first and second implantations.Type: GrantFiled: January 28, 2016Date of Patent: September 13, 2016Assignee: Toyota Jidosha Kabushiki KaishaInventors: Toru Onishi, Yuichiro Matsuura
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Publication number: 20160233130Abstract: A diode manufacturing method provided herein includes first-third implantations and a heating. The first implantation implants n-type impurities into a first range at a first depth. The second implantation implants n-type impurities into a second range including the first range as a part at a second depth shallower than the first depth. The third implantation implants p-type impurities into a third range located on both sides of the second range at a third depth shallower than the first depth at a density higher than the second implantation. The semiconductor substrate is heated in the heating so that a first p-type region (contact region) is formed in the implanted region in the third implantation and a first n-type region (pillar region) is formed in a part of the implanted region in the first and second implantations.Type: ApplicationFiled: January 28, 2016Publication date: August 11, 2016Inventors: Toru Onishi, Yuichiro Matsuura
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Publication number: 20160122784Abstract: The invention is intended to improve xylose assimilation ability and ethanol fermentation ability in a xylose-assimilating yeast into which a xylose isomerase gene has been introduced. The amount of NADH produced by the recombinant yeast into which the xylose isomerase gene had been introduced as a result of the enzymatic reaction of acetohydroxy acid reductoisomerase is lowered.Type: ApplicationFiled: June 9, 2014Publication date: May 5, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru ONISHI, Nobuki TADA, Satoshi KATAHIRA, Risa NAGURA, Nobuhiro ISHIDA
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Publication number: 20160040151Abstract: A eukaryotic cell having xylose utilization ability. Provided is a protein that has xylose isomerase activity and has an amino acid sequence including, when aligned with an amino acid sequence expressed by SEQ ID NO:1, the 1st to 6th motifs expressed respectively by SEQ ID NOs:2 to 7 from the N-terminus side in the order described, and having, in place of asparagine (N) in an amino acid sequence of the 6th motif, another amino acid.Type: ApplicationFiled: March 28, 2014Publication date: February 11, 2016Inventors: Satoshi KATAHIRA, Risa NAGURA, Kenro TOKUHIRO, Nobuhiro ISHIDA, Chie IMAMURA, Toru ONISHI, Noriko YASUTANI, Nobuki TADA
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Patent number: 9234217Abstract: This invention is intended to produce isobutanol with excellent productivity via a fermentation process. A reaction in which NADP-dependent isocitrate dehydrogenase generates NADPH from NADP is used as a source of NADPH for the reaction of converting 2-acetolactate into 2,3-dihydroxy-isovalerate in the isobutanol biosynthesis pathway.Type: GrantFiled: October 23, 2012Date of Patent: January 12, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Toru Onishi
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Publication number: 20160005843Abstract: By using an SOI substrate in which a front surface-side semiconductor layer, an insulating layer, and a back surface-side semiconductor layer are laminated in this order, vertical semiconductor devices are mass-produced. A process to be executed on a front surface of the SOI substrate is executed on the front surface. A back surface of the SOI substrate is etched so that the back surface-side semiconductor layer and the insulating layer are removed and a back surface of the front surface-side semiconductor layer is exposed. A process to be executed on the exposed back surface of the front surface-side semiconductor layer is executed on the back surface. A thickness of the front surface-side semiconductor layer of the SOI substrate can be accurately controlled, and the semiconductor devices having a semiconductor layer with the same thickness as the thickness of the front surface-side semiconductor layer are mass-produced.Type: ApplicationFiled: February 12, 2013Publication date: January 7, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yasuhiro HIRABAYASHI, Toru ONISHI, Katsuhiko NISHIWAKI, Jun SAITO
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Publication number: 20160002674Abstract: The invention is intended to metabolize acetic acid and to lower acetic acid concentration in a medium at the time of xylose assimilation and ethanol fermentation by a yeast strain having xylose-metabolizing ability. The method for producing ethanol comprises a step of culturing recombinant yeast strains resulting from introduction of a xylose isomerase gene and an acetaldehyde dehydrogenase gene into a medium containing xylose, so as to perform ethanol fermentation.Type: ApplicationFiled: February 27, 2014Publication date: January 7, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru ONISHI, Nobuki TADA, Noriko YASUTANI, Satoshi KATAHIRA, Nobuhiro ISHIDA, Risa NAGURA
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Patent number: 9214522Abstract: A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove.Type: GrantFiled: December 19, 2013Date of Patent: December 15, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kunihito Kato, Toru Onishi
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Publication number: 20150325709Abstract: A semiconductor device is provided with a semiconductor layer including Si and a Schottky electrode being in Schottky contact with at least a part of one of main surfaces of the semiconductor layer. A material of the Schottky electrode is a Al—Si alloy including at least one metal selected from the group consisting of Ti, Ta, Nb, Hf, Zr, W, Mo and V.Type: ApplicationFiled: March 13, 2015Publication date: November 12, 2015Inventors: Takahiro ITO, Toru ONISHI, Hideya YAMADERA, Satoru MACHIDA, Yusuke YAMASHITA
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Patent number: 9166029Abstract: A method for manufacturing a semiconductor device includes: forming, in element regions of a semiconductor wafer, electrodes and a insulator on peripheral part of the electrodes so that a height of the insulator is higher than that of the electrodes; forming, on the front face of the semiconductor wafer, a groove for surrounding a periphery of the electrodes with the insulator being sandwiched between the electrodes and the groove, the groove being formed so that a height of the groove is lower than that of the insulator and the groove extends to an outer circumferential edge of the semiconductor wafer; bonding adhesives onto the electrodes in the element regions so that a height of the adhesives is higher than that of the insulator, and bonding, onto the adhesives, a base material for covering the front face of the semiconductor wafer; and processing a rear face of the semiconductor wafer.Type: GrantFiled: January 9, 2014Date of Patent: October 20, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Toru Onishi
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Patent number: 9145888Abstract: A differential pressure control valve has a valve seat made of magnetic material, a valve body, and a guiding member fixed to the valve seat to guide the valve body. The valve body is located on the downstream side of the valve seat, and is seatable on the valve seat in accordance with the pressure difference between the upstream side and the downstream side to selectively open and close a valve hole. The valve body has a lid made of magnetic material and a guided member made of nonmagnetic material. The lid is seated on the valve seat to close the valve hole, and the guided member is guided by the guiding member. The valve seat or the lid has a permanent magnet, located outside the area where the valve body is seated on the valve seat, urging the valve body in the direction approaching the valve seat.Type: GrantFiled: November 22, 2011Date of Patent: September 29, 2015Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Nobuaki Hoshino, Masaki Ota, Yoshio Kimoto, Toru Onishi, Yusuke Yamazaki
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Patent number: 9133548Abstract: A TiN film forming method repeatedly performs for a plurality of substrates to be processed, a step of loading each substrate into a processing chamber, supplying a Ti-containing gas and a nitriding gas into the processing chamber, and forming a TiN film on a surface of the substrate by generating a plasma of the supplied gases. The TiN film forming method includes a Ti film forming step of forming a Ti film by supplying a processing gas containing Ti-containing gas into the processing chamber in a state where no substrate exists in the processing chamber after the TiN films are formed on a predetermined number of the substrates.Type: GrantFiled: January 15, 2014Date of Patent: September 15, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Hideaki Yamasaki, Shinya Okabe, Takeshi Yamamoto, Toru Onishi
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Publication number: 20150093263Abstract: A swash plate type variable displacement compressor includes a collection and supply mechanism. The collection and supply mechanism has collection passages, supply passages, an annular space, an inlet port, and an outlet port. The inlet port is communicable with a working collection passage of the collection passages. The outlet port is communicable with a working supply passage of the supply passages. When the inclination angle of the swash plate is maximum, residual refrigerant gas in a compression chamber of collection phase is collected through the working collection passage and the collected refrigerant gas is supplied to a compression chamber of supply phase. On the other hand, when the inclination angle is less than the maximum, residual refrigerant gas is supplied no more into the supply-phase compression chamber.Type: ApplicationFiled: September 23, 2014Publication date: April 2, 2015Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Yoshio KIMOTO, Toru ONISHI, Kengo SAKAKIBARA, Yuki YOKOI, Takahisa BAN, Ryo MATSUBARA, Noriyuki SHINTOKU
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Publication number: 20150008479Abstract: An IGBT manufacturing method is provided. The IGBT has an n-type emitter region, a p-type top body region, an n-type intermediate region, a p-type bottom body region, an n-type drift region, a p-type collector region, trenches penetrating the emitter region, the top body region, the intermediate region and the bottom body region from an upper surface of a semiconductor substrate and reaching the drift region, and gate electrodes formed in the trenches. The method includes forming the trenches on the upper surface of the semiconductor substrate, forming the insulating film in the trenches, forming an electrode layer on the semiconductor substrate and in the trenches after forming the insulating film, planarizing an upper surface of the electrode layer, and implanting n-type impurities to a depth of the intermediate region from the upper surface side of the semiconductor substrate after planarizing the upper surface of the electrode layer.Type: ApplicationFiled: February 14, 2012Publication date: January 8, 2015Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takehiro Kato, Toru Onishi
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Patent number: 8859248Abstract: This invention provides a method for improving the xylose-metabolizing ability of a yeast strain having xylose-metabolizing ability. The method comprises steps of: soaking the yeast strain having xylose-metabolizing ability in an acetic-acid-containing solution; and then, culturing the yeast strain in a xylose-containing medium to perform ethanol fermentation.Type: GrantFiled: November 11, 2010Date of Patent: October 14, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventors: Toru Onishi, Emiko Tominaga, Noriko Yasutani
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Publication number: 20140273136Abstract: The invention is intended to metabolize acetic acid and to lower acetic acid concentration in a medium at the time of xylose assimilation and ethanol fermentation by a yeast strain having xylose-metabolizing ability. To this end, a recombinant yeast strain having xylose-metabolizing ability and comprising an acetaldehyde dehydrogenase gene introduced thereinto is cultured in a medium containing cellulose, cellulase, and xylose to perform ethanol fermentation.Type: ApplicationFiled: October 23, 2012Publication date: September 18, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Toru Onishi