Patents by Inventor Toru Takayama

Toru Takayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8508682
    Abstract: The present invention provides a simplifying method for a peeling process as well as peeling and transcribing to a large-size substrate uniformly. A feature of the present invention is to peel a first adhesive and to cure a second adhesive at the same time in a peeling process, thereby to simplify a manufacturing process. In addition, the present invention is to devise the timing of transcribing a peel-off layer in which up to an electrode of a semiconductor are formed to a predetermined substrate. In particular, a feature is that peeling is performed by using a pressure difference in the case that peeling is performed with a state in which plural semiconductor elements are formed on a large-size substrate.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: August 13, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno
  • Publication number: 20130194003
    Abstract: The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 1, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toru TAKAYAMA, Hirotoshi Aizawa, Shinya Takeshita
  • Patent number: 8497525
    Abstract: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: July 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Shunpei Yamazaki, Toru Takayama
  • Patent number: 8497720
    Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
  • Patent number: 8492862
    Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
  • Patent number: 8482011
    Abstract: The present invention provides a structure in which a pixel region 13 is surrounded by a first sealing material (having higher viscosity than a second sealing material) 16 including a spacer (filler, minute particles and/or the like) which maintains a gap between the two substrates, filled with a few drops of the transparent second sealing material 17a which is spread in the region; and sealed by using the first sealing material 16 and the second sealing material 17.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Toru Takayama, Yumiko Ohno
  • Patent number: 8470647
    Abstract: There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: June 25, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Koji Ono, Toru Takayama, Tatsuya Arao, Shunpei Yamazaki
  • Patent number: 8461013
    Abstract: An IC card is more expensive than a magnetic card, and an electronic tag is also more expensive as a substitute for bar codes. Therefore, the present invention provides an extremely thin integrated circuit that can be mass-produced at low cost unlike a chip of a conventional silicon wafer, and a manufacturing method thereof. One feature of the present invention is that a thin integrated circuit is formed by a formation method that can form a pattern selectively, on a glass substrate, a quartz substrate, a stainless substrate, a substrate made of synthetic resin having flexibility, such as acryl, or the like except for a bulk substrate. Further, another feature of the present invention is that an ID chip in which a thin film integrated circuit and an antenna according to the present invention are mounted is formed.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Gen Fujii, Junya Maruyama, Toru Takayama, Yumiko Fukumoto, Yasuyuki Arai
  • Patent number: 8441102
    Abstract: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100. An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107, thereby forming a high frequency module or the like.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno, Yuugo Goto, Hideaki Kuwabara
  • Patent number: 8415660
    Abstract: The present invention has an object of providing a light-emitting device including an OLED formed on a plastic substrate, which prevents degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light-emitting layer in the OLED (“barrier films”) and a film having a smaller stress than the barrier films (“stress relaxing film”), the film being interposed between the barrier films, are provided. Owing to a laminate structure, if a crack occurs in one of the barrier films, the other barrier film(s) can prevent moisture or oxygen from penetrating into the organic light emitting layer. The stress relaxing film, which has a smaller stress than the barrier films, is interposed between the barrier films, making it possible to reduce stress of the entire sealing film. Therefore, a crack due to stress hardly occurs.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mai Akiba
  • Patent number: 8415208
    Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Mayumi Mizukami, Shunpei Yamazaki
  • Patent number: 8415679
    Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Publication number: 20130084205
    Abstract: The present invention provides a steel which simultaneously satisfies a plurality of characteristics, specifically, a steel for tubes with excellent sulfide stress cracking resistance, including, C: 0.2 to 0.7%; Si: 0.01 to 0.8%; Mn: 0.1 to 1.5%; S: not more than 0.005%; P: not more than 0.03%; Al: 0.0005 to 0.1%; Ti: 0.005 to 0.05%; Ca: 0.0004 to 0.005%; N: not more than 0.007%; Cr: 0. 1 to 1.5%; and Mo: 0.2 to 1.0%; the balance being Fe, Mg and impurities, being characterized in that: the content of Mg is not less than 1.0 ppm and not more than 5.0 ppm; and inclusions of not less than 50% of the total number of those in steel have such a morphology that Mg—Al—O-based oxides exist at the central part of the inclusion, Ca—Al-based oxides enclose the Mg—Al—O-based oxides, and Ti-containing-carbonitrides further exist on a periphery of the Ca—Al-based oxides.
    Type: Application
    Filed: May 25, 2011
    Publication date: April 4, 2013
    Applicant: NIPPON STEEL & SUMMITOMA METALCORPORATION
    Inventors: Mitsuhiro Numata, Tomohiko Omura, Masayuki Morimoto, Toru Takayama, Atsushi Soma
  • Patent number: 8390019
    Abstract: A semiconductor device in which degradation due to permeation of water and oxygen can be limited, e.g., a light emitting device having an organic light emitting device (OLED) formed on a plastic substrate, and a liquid crystal display using a plastic substrate. A layer to be debonded, containing elements, is formed on a substrate, bonded to a supporting member, and debonded from the substrate. A thin film is thereafter formed on the debonded layer. The debonded layer with the thin film is adhered to a transfer member. Cracks caused in the debonded layer at the time of debonding are thereby repaired. As the thin film in contact with the debonded layer, a film having thermal conductivity, e.g., film of aluminum nitride or aluminum nitroxide is used. This film dissipates heat from the elements and has the effect of preventing deformation and change in quality of the transfer member, e.g., a plastic substrate.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Mayumi Mizukami
  • Patent number: 8384699
    Abstract: The present invention intends to realize a narrow frame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno, Yasuyuki Arai, Noriko Shibata
  • Patent number: 8377799
    Abstract: An object of the present invention is to provide an SOI substrate including a semiconductor layer which is efficiently planarized. A method for manufacturing an SOI substrate includes a step of irradiating a bond substrate with an accelerated ion to form an embrittlement region; a step of bonding the bond substrate and the base substrate with an insulating layer positioned therebetween; a step of splitting the bond substrate at the embrittlement region to leave a semiconductor layer bonded to the base substrate; a step of disposing the semiconductor layer in front of a semiconductor target containing the same semiconductor material as the semiconductor layer; and a step of alternately irradiating the surface of the semiconductor layer and the semiconductor target with a rare gas ion, so that the surface of the semiconductor layer is planarized.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: February 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mizuho Sato, Noriaki Uto
  • Patent number: 8367440
    Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Mayumi Mizukami, Shunpei Yamazaki
  • Publication number: 20130029447
    Abstract: A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed.
    Type: Application
    Filed: August 16, 2012
    Publication date: January 31, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Junya MARUYAMA, Toru TAKAYAMA, Yumiko OHNO, Shunpei YAMAZAKI
  • Patent number: 8362487
    Abstract: A light emitting element having an organic compound, which can be extended its longevity is provided. According to the present invention, there is provided a constitution in which, in order to protect a light emitting element from moisture, an inorganic insulating film 312a, a stress relaxation layer 312b having transparency and a hygroscopic property, and an inorganic insulating film 312c are repeatedly laminated over a cathode. The stress relaxation layer 312b having transparency and the hygroscopic property uses at least one film selected from the group consisting of a film comprising a same material as that of a layer 310, containing an organic compound, sandwiched between a cathode and an anode, a layer capable of being formed by vapor deposition, and a layer capable of being formed by coating.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama
  • Patent number: 8357611
    Abstract: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Keiji Sato, Shunpei Yamazaki