Patents by Inventor Toshiaki Iwamatsu
Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145467Abstract: An object is to provide a technology capable of predicting fluctuation in electrical characteristics of vertical semiconductor transistors when operated in the market. The semiconductor device includes a vertical semiconductor transistor and a horizontal semiconductor transistor provided on the same semiconductor base. A gate electrode of the vertical semiconductor transistor and a gate electrode of the horizontal semiconductor transistor are electrically connected. A source electrode of the vertical semiconductor transistor and a source electrode of the horizontal semiconductor transistor are electrically connected.Type: ApplicationFiled: March 29, 2021Publication date: May 2, 2024Applicant: Mitsubishi Electric CorporationInventor: Toshiaki IWAMATSU
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Publication number: 20230282647Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.Type: ApplicationFiled: May 15, 2023Publication date: September 7, 2023Inventors: Takaaki TSUNOMURA, Yoshiki YAMAMOTO, Masaaki SHINOHARA, Toshiaki IWAMATSU, Hidekazu ODA
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Publication number: 20230253456Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
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Publication number: 20230246101Abstract: A semiconductor device according to the present disclosure includes: a diffusion protection layer in contact with a bottom surface of a gate trench provided in an active region; a termination protection layer in contact with a bottom surface of a termination trench provided in a termination region and having a width larger than the gate trench; a gate insulating film and gate wires provided in the gate trench and the termination trench; and a source electrode electrically connected to the diffusion protection layer, and the termination protection layer, wherein a termination insulating film that has a thickness equal to or larger than the thickness of the gate insulating film is formed in the termination trench, and the gate wires are formed in grooves in two or more portions with the termination insulating film interposed therebetween, surrounded by an outer peripheral wall of the termination trench and the termination insulating film.Type: ApplicationFiled: September 30, 2020Publication date: August 3, 2023Applicant: Mitsubishi Electric CorporationInventor: Toshiaki IWAMATSU
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Patent number: 11695012Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.Type: GrantFiled: July 14, 2020Date of Patent: July 4, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
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Patent number: 11695014Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.Type: GrantFiled: November 17, 2021Date of Patent: July 4, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryuta Tsuchiya, Toshiaki Iwamatsu
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Patent number: 11658211Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: GrantFiled: April 7, 2021Date of Patent: May 23, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Publication number: 20230006045Abstract: The present disclosure has an object of providing a silicon carbide semiconductor device with high productivity which prevents characteristic degradation occurring when a large current is applied to a body diode. A structure including a SiC substrate, a buffer layer, and a drift layer is classified into an active region through which a current flows with application of a voltage to the SiC-MOSFET, and a breakdown voltage support region around a periphery of the active region in a plan view. The active region is classified into a first active region in a center portion, and a second active region between the first active region and the breakdown voltage support region in the plan view. Lifetimes of minority carriers in the second active region and the breakdown voltage support region are shorter than that in the first active region.Type: ApplicationFiled: January 27, 2020Publication date: January 5, 2023Applicant: Mitsubishi Electric CorporationInventors: Naoyuki KAWABATA, Yuichi NAGAHISA, Takanori TANAKA, Toshiaki IWAMATSU
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Publication number: 20220077191Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Ryuta TSUCHIYA, Toshiaki IWAMATSU
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Patent number: 11211406Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.Type: GrantFiled: August 30, 2016Date of Patent: December 28, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryuta Tsuchiya, Toshiaki Iwamatsu
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Publication number: 20210257459Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: April 7, 2021Publication date: August 19, 2021Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
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Publication number: 20200343268Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Inventors: Takaaki TSUNOMURA, Yoshiki YAMAMOTO, Masaaki SHINOHARA, Toshiaki IWAMATSU, Hidekazu ODA
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Patent number: 10756115Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.Type: GrantFiled: October 31, 2019Date of Patent: August 25, 2020Assignee: Renesas Electronics CorporationInventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
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Patent number: 10665679Abstract: A silicon carbide semiconductor device includes: an n-type drift layer 2 provided within an SiC layer 30; a plurality of p-type well regions 3; a JFET region JR serving as a part of the drift layer 2 sandwiched between the well regions 3; and a gate insulating film 6 and a gate electrode 7 at least covering the JFET region JR. The gate insulating film 6 and the gate electrode 7 include a different-element-containing region 10 containing an element that is different from elements constituting the gate insulating film 6 and the gate electrode 7.Type: GrantFiled: November 28, 2016Date of Patent: May 26, 2020Assignee: Mitsubishi Electric CorporationInventors: Tomokatsu Watanabe, Shiro Hino, Yusuke Yamashiro, Toshiaki Iwamatsu
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Publication number: 20200066757Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Inventors: Takaaki TSUNOMURA, Yoshiki YAMAMOTO, Masaaki SHINOHARA, Toshiaki IWAMATSU, Hidekazu ODA
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Patent number: 10559653Abstract: The technique disclosed in the Description relates to a technique preventing dielectric breakdown while a silicon carbide semiconductor device is OFF, without degrading process throughput or yield. The silicon carbide semiconductor device relating to the technique disclosed in the Description includes a drift layer of a first conductivity type, a threading dislocation provided to penetrate the drift layer, and an electric-field reduction region of a second conductivity type disposed in a position in the surface layer of the drift layer, the position corresponding to the threading dislocation. The electric-field reduction region is an epitaxial layer.Type: GrantFiled: May 23, 2017Date of Patent: February 11, 2020Assignee: Mitsubishi Electric CorporationInventors: Tomokatsu Watanabe, Shiro Hino, Yusuke Yamashiro, Toshiaki Iwamatsu
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Publication number: 20200013857Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Applicant: Renesas Electronics CorporationInventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
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Patent number: 10510844Abstract: Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region bType: GrantFiled: June 22, 2017Date of Patent: December 17, 2019Assignee: Mitsubishi Electric CorporationInventors: Munetaka Noguchi, Toshiaki Iwamatsu
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Patent number: 10510775Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.Type: GrantFiled: September 5, 2017Date of Patent: December 17, 2019Assignee: Renesas Electronics CorporationInventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
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Patent number: 10461158Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: GrantFiled: October 3, 2018Date of Patent: October 29, 2019Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura