Patents by Inventor Toshiaki Iwamatsu
Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9184053Abstract: An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.Type: GrantFiled: January 7, 2013Date of Patent: November 10, 2015Assignee: Renesas Electronics CorporationInventors: Hirofumi Shinohara, Hiromasa Yoshimori, Toshiaki Iwamatsu, Hidekazu Oda
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Patent number: 9166041Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.Type: GrantFiled: August 14, 2014Date of Patent: October 20, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu
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Publication number: 20150287746Abstract: In a step F2, an isolation region and an element formation region are formed in an SOI substrate. In a step F3, an SOI region and a bulk region are formed. Here, an isolation insulating film of the isolation region is exposed along the entire perimeter of a sidewall of a step between the SOI region and the bulk region. In a step F4, a gate electrode is formed. In a step F5, extension implantation of a bulk transistor is carried out. Here, treatment for preventing an impurity for extension implantation from being implanted into the SOI region is performed. In a step F6, an elevated epitaxial layer is formed in the SOI region.Type: ApplicationFiled: March 31, 2015Publication date: October 8, 2015Inventors: Hiroki SHINKAWATA, Toshiaki IWAMATSU
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Patent number: 9142567Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.Type: GrantFiled: February 5, 2015Date of Patent: September 22, 2015Assignee: Renesas Electronics CorporationInventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama
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Patent number: 9130039Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.Type: GrantFiled: August 8, 2013Date of Patent: September 8, 2015Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Publication number: 20150221668Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.Type: ApplicationFiled: February 5, 2015Publication date: August 6, 2015Inventors: Katsuyuki HORITA, Toshiaki IWAMATSU, Hideki MAKIYAMA
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Publication number: 20150221560Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.Type: ApplicationFiled: April 15, 2015Publication date: August 6, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Katsuyuki HORITA, Toshiaki IWAMATSU, Hideki MAKIYAMA, Yoshiki YAMAMOTO
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Patent number: 9054102Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.Type: GrantFiled: July 11, 2014Date of Patent: June 9, 2015Assignee: Renesas Electronics CorporationInventors: Hiromasa Yoshimori, Hirofumi Shinohara, Toshiaki Iwamatsu
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Publication number: 20150137239Abstract: To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.Type: ApplicationFiled: August 27, 2014Publication date: May 21, 2015Inventors: Hirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu
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Patent number: 9029951Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.Type: GrantFiled: July 22, 2012Date of Patent: May 12, 2015Assignee: Renesas Electronics CorporationInventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama
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Patent number: 9024386Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.Type: GrantFiled: November 15, 2012Date of Patent: May 5, 2015Assignee: Renesas Electronics CorporationInventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama, Yoshiki Yamamoto
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Publication number: 20150111348Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Publication number: 20150084064Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.Type: ApplicationFiled: May 18, 2012Publication date: March 26, 2015Inventors: Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Toshiaki Iwamatsu
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Patent number: 8975699Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.Type: GrantFiled: September 24, 2014Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Toshiaki Iwamatsu, Katsuyuki Horita, Hideki Makiyama
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Publication number: 20150061006Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.Type: ApplicationFiled: August 14, 2014Publication date: March 5, 2015Inventors: Hirofumi SHINOHARA, Hidekazu ODA, Toshiaki IWAMATSU
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Patent number: 8941178Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: GrantFiled: January 23, 2013Date of Patent: January 27, 2015Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Publication number: 20150008522Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.Type: ApplicationFiled: September 24, 2014Publication date: January 8, 2015Applicant: Renesas Electronics CorporationInventors: Toshiaki IWAMATSU, Katsuyuki HORITA, Hideki MAKIYAMA
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Publication number: 20140375379Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.Type: ApplicationFiled: June 20, 2014Publication date: December 25, 2014Inventors: Hideki MAKIYAMA, Toshiaki IWAMATSU
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Publication number: 20140319618Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.Type: ApplicationFiled: July 11, 2014Publication date: October 30, 2014Inventors: Hiromasa YOSHIMORI, Hirofumi Shinohara, Toshiaki Iwamatsu
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Patent number: 8872267Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.Type: GrantFiled: November 13, 2012Date of Patent: October 28, 2014Assignee: Renesas Electronics CorporationInventors: Toshiaki Iwamatsu, Katsuyuki Horita, Hideki Makiyama