Patents by Inventor Toshiaki Iwamatsu

Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150111348
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Publication number: 20150084064
    Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.
    Type: Application
    Filed: May 18, 2012
    Publication date: March 26, 2015
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Toshiaki Iwamatsu
  • Patent number: 8975699
    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Katsuyuki Horita, Hideki Makiyama
  • Publication number: 20150061006
    Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.
    Type: Application
    Filed: August 14, 2014
    Publication date: March 5, 2015
    Inventors: Hirofumi SHINOHARA, Hidekazu ODA, Toshiaki IWAMATSU
  • Patent number: 8941178
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Publication number: 20150008522
    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Toshiaki IWAMATSU, Katsuyuki HORITA, Hideki MAKIYAMA
  • Publication number: 20140375379
    Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 25, 2014
    Inventors: Hideki MAKIYAMA, Toshiaki IWAMATSU
  • Publication number: 20140319618
    Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.
    Type: Application
    Filed: July 11, 2014
    Publication date: October 30, 2014
    Inventors: Hiromasa YOSHIMORI, Hirofumi Shinohara, Toshiaki Iwamatsu
  • Patent number: 8872267
    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Katsuyuki Horita, Hideki Makiyama
  • Patent number: 8809959
    Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromasa Yoshimori, Hirofumi Shinohara, Toshiaki Iwamatsu
  • Publication number: 20140203364
    Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 24, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaaki TSUNOMURA, Toshiaki IWAMATSU
  • Patent number: 8754471
    Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: June 17, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Kozo Ishikawa, Masashi Kitazawa, Kiyoshi Hayashi, Takahiro Maruyama, Masaaki Shinohara, Kenji Kawai
  • Publication number: 20140042552
    Abstract: Provided is a semiconductor device having an insulating gate field effect transistor equipped with a metal oxide film in a portion, on the side of a source region, between a gate insulating film and a gate electrode. The metal oxide film is provided above a p+ type semiconductor region for punch-through stopper so as to cover the entire region thereof. Such a metal oxide film contributes to a decrease in the impurity concentration of the p+ type semiconductor region, making it possible to reduce variations in the threshold voltage of the transistor. On the side of a drain region, the gate insulating film is formed as a single film without stacking the metal oxide film thereon. As a result, the resulting transistor can escape deterioration in reliability which will otherwise occur due to hot carriers on the side of the end of the drain region.
    Type: Application
    Filed: August 4, 2013
    Publication date: February 13, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hiromasa Yoshimori, Toshiaki Iwamatsu
  • Publication number: 20140042529
    Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 13, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Patent number: 8558312
    Abstract: A bulk & SOI hybrid CMIS device, in which an I/O bulk part and a core logic SOI part are mounted, needs a number of gate stacks to optimize threshold voltage control and causes a problem that the process and structure become complicated. The present invention adjusts the threshold voltage of MISFET at the corresponding part by introducing impurities into any of back gate semiconductor regions, in an SOI semiconductor CMISFET integrated circuit device having a high-k gate insulating film and a metal gate electrode.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: October 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiaki Iwamatsu
  • Publication number: 20130264644
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 10, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Publication number: 20130230964
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 5, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira Imai, Toshiaki Iwamatsu, Akihiro Nakae
  • Patent number: 8513058
    Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Yuichi Hirano
  • Patent number: 8492230
    Abstract: To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kozo Ishikawa, Masaaki Shinohara, Toshiaki Iwamatsu
  • Publication number: 20130020644
    Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.
    Type: Application
    Filed: July 22, 2012
    Publication date: January 24, 2013
    Inventors: Katsuyuki HORITA, Toshiaki IWAMATSU, Hideki MAKIYAMA