Patents by Inventor Toshiaki Komukai

Toshiaki Komukai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11806901
    Abstract: According to one embodiment, a template is provided with a transferring pattern on a first surface of a substrate. The transferring pattern includes a first projecting portion that projects from the first surface with a first height and extends in a first direction along the first surface, a second projecting portion that projects from the first surface with a second height higher than the first height and extends in a second direction along the first surface, a first columnar portion that is arranged at a position overlapping with the first projecting portion and has a top surface with a third height higher than the second height as a height from the first surface, and a second columnar portion that is arranged at a position overlapping with the second projecting portion and has a top surface with the third height as a height from the first surface.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: November 7, 2023
    Assignee: Kioxia Corporation
    Inventors: Kazuhiro Takahata, Toshiaki Komukai, Hideki Kanai
  • Publication number: 20230307287
    Abstract: A method of manufacturing a semiconductor device includes applying a resin on a first surface of a first layer, the first layer comprising a first hole having a first depth and a second hole having a second depth, forming a pattern on the resin, the pattern comprising a convex part above the first hole a diameter of the convex part being smaller than a diameter of an opening of the first hole, forming a protecting layer exposing a part of the convex part, removing the resin in the first hole, the resin in the hole being connected with the convex part, and processing the first hole to form a third hole connecting with the first hole and having a third depth in the first layer below the first hole.
    Type: Application
    Filed: September 8, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Toshiaki Komukai, Motofumi Komori
  • Publication number: 20220080627
    Abstract: According to one embodiment, a template is provided with a transferring pattern on a first surface of a substrate. The transferring pattern includes a first projecting portion that projects from the first surface with a first height and extends in a first direction along the first surface, a second projecting portion that projects from the first surface with a second height higher than the first height and extends in a second direction along the first surface, a first columnar portion that is arranged at a position overlapping with the first projecting portion and has a top surface with a third height higher than the second height as a height from the first surface, and a second columnar portion that is arranged at a position overlapping with the second projecting portion and has a top surface with the third height as a height from the first surface.
    Type: Application
    Filed: March 12, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazuhiro TAKAHATA, Toshiaki KOMUKAI, Hideki KANAI
  • Publication number: 20220050392
    Abstract: A template includes: a base material having a principal surface; a mesa structure provided on the principal surface and having a first surface; and a silicon film that is provided on the first surface of the mesa structure, has a projection-and-depression pattern, and is made of a material different from a material for the base material.
    Type: Application
    Filed: August 11, 2021
    Publication date: February 17, 2022
    Applicant: Kioxia Corporation
    Inventor: Toshiaki KOMUKAI
  • Patent number: 10877372
    Abstract: A pattern forming method, including an imprinting process is provided. The method includes preparing a substrate having an organic film; forming a surface film, containing at least one of a metal or a semiconductor, in or on the surface of the organic film. The method further includes forming an inorganic film on the surface film; applying an organic mask material onto the inorganic film, and pressing a template having a fine pattern against the organic mask material to form a mask pattern; processing the inorganic film using the mask pattern as a mask; and removing the mask pattern. The organic mask material, when pressed by the template, is cured or solidified by being exposed to an ultraviolet light source. The solidified organic mask includes an overflow portion removable by plasma asking and exposing the surface film underneath.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiaki Komukai
  • Publication number: 20200012187
    Abstract: A pattern forming method, including an imprinting process is provided. The method includes preparing a substrate having an organic film; forming a surface film, containing at least one of a metal or a semiconductor, in or on the surface of the organic film. The method further includes forming an inorganic film on the surface film; applying an organic mask material onto the inorganic film, and pressing a template having a fine pattern against the organic mask material to form a mask pattern; processing the inorganic film using the mask pattern as a mask; and removing the mask pattern. The organic mask material, when pressed by the template, is cured or solidified by being exposed to an ultraviolet light source. The solidified organic mask includes an overflow portion removable by plasma asking and exposing the surface film underneath.
    Type: Application
    Filed: February 25, 2019
    Publication date: January 9, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiaki KOMUKAI
  • Patent number: 10459335
    Abstract: According to an embodiment, a template is provided which includes a template substrate, and a device formation pattern and an alignment mark provided on a common surface of the template substrate. The alignment mark includes a refraction layer provided at a bottom of a first concave pattern provided on the template substrate, and an insulating layer filling the first concave pattern provided with the refraction layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Toshiaki Komukai
  • Publication number: 20180267400
    Abstract: According to an embodiment, a template is provided which includes a template substrate, and a device formation pattern and an alignment mark provided on a common surface of the template substrate. The alignment mark includes a refraction layer provided at a bottom of a first concave pattern provided on the template substrate, and an insulating layer filling the first concave pattern provided with the refraction layer.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 20, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Toshiaki KOMUKAI
  • Publication number: 20120133010
    Abstract: According to one embodiment, a semiconductor device includes: a through-hole formed in a semiconductor layer; a through-hole insulting layer formed on a sidewall of the through-hole to retract from a front surface of the semiconductor layer; a through-electrode embedded in the through-hole via the through-hole insulating layer; and a sidewall insulating film formed on a sidewall of the through-electrode to be embedded in a retracting section of the through-hole insulating layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiaki KOMUKAI
  • Patent number: 7858465
    Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki Komukai, Hideaki Harakawa
  • Patent number: 7675183
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
  • Patent number: 7479433
    Abstract: A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: January 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki Komukai, Hideaki Harakawa
  • Publication number: 20080237863
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 2, 2008
    Applicant: Kabushiki Kaisha Tosiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
  • Publication number: 20080197398
    Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 21, 2008
    Inventors: Toshiaki KOMUKAI, Hideaki Harakawa
  • Publication number: 20070120185
    Abstract: A method for manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate; forming an impurity diffusion layer in a region which includes an end of an active area adjacent to the isolation region; depositing a metal film on the semiconductor substrate; removing at least part of the metal film on the isolation region; and subjecting the metal film and the semiconductor substrate to a heat treatment, thereby forming a silicide film on the impurity diffusion layer in a self-aligned fashion.
    Type: Application
    Filed: June 7, 2006
    Publication date: May 31, 2007
    Inventors: Toshiaki Komukai, Hideaki Harakawa
  • Publication number: 20060270131
    Abstract: A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.
    Type: Application
    Filed: May 5, 2006
    Publication date: November 30, 2006
    Inventors: Toshiaki Komukai, Hideaki Harakawa
  • Publication number: 20060113674
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Application
    Filed: January 11, 2006
    Publication date: June 1, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
  • Publication number: 20050191817
    Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a gate electrode formed on the substrate via a gate insulating film and containing silicon, an insulating offset spacer formed on a side surface of the gate electrode and having an upper surface lower than an upper surface of the gate electrode, an insulating sidewall spacer formed on an upper side surface of the gate electrode and on a side surface of the offset spacer by using a material different from the offset spacer, a lightly doped impurity diffusion layer formed in the semiconductor substrate so as to sandwich the gate electrode, a heavily doped impurity diffusion layer formed in the semiconductor substrate in a position deeper than the lightly doped impurity diffusion layer, so as to sandwich the gate electrode and sidewall spacer, and a silicide film formed on the gate electrode.
    Type: Application
    Filed: February 25, 2005
    Publication date: September 1, 2005
    Inventors: Toshiaki Komukai, Hideaki Harakawa
  • Publication number: 20040159951
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 19, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
  • Patent number: 6727593
    Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: April 27, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai