Patents by Inventor Toshiaki Komukai
Toshiaki Komukai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11806901Abstract: According to one embodiment, a template is provided with a transferring pattern on a first surface of a substrate. The transferring pattern includes a first projecting portion that projects from the first surface with a first height and extends in a first direction along the first surface, a second projecting portion that projects from the first surface with a second height higher than the first height and extends in a second direction along the first surface, a first columnar portion that is arranged at a position overlapping with the first projecting portion and has a top surface with a third height higher than the second height as a height from the first surface, and a second columnar portion that is arranged at a position overlapping with the second projecting portion and has a top surface with the third height as a height from the first surface.Type: GrantFiled: March 12, 2021Date of Patent: November 7, 2023Assignee: Kioxia CorporationInventors: Kazuhiro Takahata, Toshiaki Komukai, Hideki Kanai
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Publication number: 20230307287Abstract: A method of manufacturing a semiconductor device includes applying a resin on a first surface of a first layer, the first layer comprising a first hole having a first depth and a second hole having a second depth, forming a pattern on the resin, the pattern comprising a convex part above the first hole a diameter of the convex part being smaller than a diameter of an opening of the first hole, forming a protecting layer exposing a part of the convex part, removing the resin in the first hole, the resin in the hole being connected with the convex part, and processing the first hole to form a third hole connecting with the first hole and having a third depth in the first layer below the first hole.Type: ApplicationFiled: September 8, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Toshiaki Komukai, Motofumi Komori
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Publication number: 20220080627Abstract: According to one embodiment, a template is provided with a transferring pattern on a first surface of a substrate. The transferring pattern includes a first projecting portion that projects from the first surface with a first height and extends in a first direction along the first surface, a second projecting portion that projects from the first surface with a second height higher than the first height and extends in a second direction along the first surface, a first columnar portion that is arranged at a position overlapping with the first projecting portion and has a top surface with a third height higher than the second height as a height from the first surface, and a second columnar portion that is arranged at a position overlapping with the second projecting portion and has a top surface with the third height as a height from the first surface.Type: ApplicationFiled: March 12, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Kazuhiro TAKAHATA, Toshiaki KOMUKAI, Hideki KANAI
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Publication number: 20220050392Abstract: A template includes: a base material having a principal surface; a mesa structure provided on the principal surface and having a first surface; and a silicon film that is provided on the first surface of the mesa structure, has a projection-and-depression pattern, and is made of a material different from a material for the base material.Type: ApplicationFiled: August 11, 2021Publication date: February 17, 2022Applicant: Kioxia CorporationInventor: Toshiaki KOMUKAI
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Patent number: 10877372Abstract: A pattern forming method, including an imprinting process is provided. The method includes preparing a substrate having an organic film; forming a surface film, containing at least one of a metal or a semiconductor, in or on the surface of the organic film. The method further includes forming an inorganic film on the surface film; applying an organic mask material onto the inorganic film, and pressing a template having a fine pattern against the organic mask material to form a mask pattern; processing the inorganic film using the mask pattern as a mask; and removing the mask pattern. The organic mask material, when pressed by the template, is cured or solidified by being exposed to an ultraviolet light source. The solidified organic mask includes an overflow portion removable by plasma asking and exposing the surface film underneath.Type: GrantFiled: February 25, 2019Date of Patent: December 29, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Toshiaki Komukai
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Publication number: 20200012187Abstract: A pattern forming method, including an imprinting process is provided. The method includes preparing a substrate having an organic film; forming a surface film, containing at least one of a metal or a semiconductor, in or on the surface of the organic film. The method further includes forming an inorganic film on the surface film; applying an organic mask material onto the inorganic film, and pressing a template having a fine pattern against the organic mask material to form a mask pattern; processing the inorganic film using the mask pattern as a mask; and removing the mask pattern. The organic mask material, when pressed by the template, is cured or solidified by being exposed to an ultraviolet light source. The solidified organic mask includes an overflow portion removable by plasma asking and exposing the surface film underneath.Type: ApplicationFiled: February 25, 2019Publication date: January 9, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Toshiaki KOMUKAI
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Patent number: 10459335Abstract: According to an embodiment, a template is provided which includes a template substrate, and a device formation pattern and an alignment mark provided on a common surface of the template substrate. The alignment mark includes a refraction layer provided at a bottom of a first concave pattern provided on the template substrate, and an insulating layer filling the first concave pattern provided with the refraction layer.Type: GrantFiled: September 7, 2017Date of Patent: October 29, 2019Assignee: Toshiba Memory CorporationInventor: Toshiaki Komukai
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Publication number: 20180267400Abstract: According to an embodiment, a template is provided which includes a template substrate, and a device formation pattern and an alignment mark provided on a common surface of the template substrate. The alignment mark includes a refraction layer provided at a bottom of a first concave pattern provided on the template substrate, and an insulating layer filling the first concave pattern provided with the refraction layer.Type: ApplicationFiled: September 7, 2017Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventor: Toshiaki KOMUKAI
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Publication number: 20120133010Abstract: According to one embodiment, a semiconductor device includes: a through-hole formed in a semiconductor layer; a through-hole insulting layer formed on a sidewall of the through-hole to retract from a front surface of the semiconductor layer; a through-electrode embedded in the through-hole via the through-hole insulating layer; and a sidewall insulating film formed on a sidewall of the through-electrode to be embedded in a retracting section of the through-hole insulating layer.Type: ApplicationFiled: September 21, 2011Publication date: May 31, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Toshiaki KOMUKAI
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Patent number: 7858465Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.Type: GrantFiled: February 14, 2008Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Komukai, Hideaki Harakawa
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Patent number: 7675183Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.Type: GrantFiled: April 22, 2008Date of Patent: March 9, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
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Patent number: 7479433Abstract: A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.Type: GrantFiled: May 5, 2006Date of Patent: January 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Komukai, Hideaki Harakawa
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Publication number: 20080237863Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.Type: ApplicationFiled: April 22, 2008Publication date: October 2, 2008Applicant: Kabushiki Kaisha TosibaInventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
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Publication number: 20080197398Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.Type: ApplicationFiled: February 14, 2008Publication date: August 21, 2008Inventors: Toshiaki KOMUKAI, Hideaki Harakawa
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Publication number: 20070120185Abstract: A method for manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate; forming an impurity diffusion layer in a region which includes an end of an active area adjacent to the isolation region; depositing a metal film on the semiconductor substrate; removing at least part of the metal film on the isolation region; and subjecting the metal film and the semiconductor substrate to a heat treatment, thereby forming a silicide film on the impurity diffusion layer in a self-aligned fashion.Type: ApplicationFiled: June 7, 2006Publication date: May 31, 2007Inventors: Toshiaki Komukai, Hideaki Harakawa
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Publication number: 20060270131Abstract: A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.Type: ApplicationFiled: May 5, 2006Publication date: November 30, 2006Inventors: Toshiaki Komukai, Hideaki Harakawa
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Publication number: 20060113674Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.Type: ApplicationFiled: January 11, 2006Publication date: June 1, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
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Publication number: 20050191817Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a gate electrode formed on the substrate via a gate insulating film and containing silicon, an insulating offset spacer formed on a side surface of the gate electrode and having an upper surface lower than an upper surface of the gate electrode, an insulating sidewall spacer formed on an upper side surface of the gate electrode and on a side surface of the offset spacer by using a material different from the offset spacer, a lightly doped impurity diffusion layer formed in the semiconductor substrate so as to sandwich the gate electrode, a heavily doped impurity diffusion layer formed in the semiconductor substrate in a position deeper than the lightly doped impurity diffusion layer, so as to sandwich the gate electrode and sidewall spacer, and a silicide film formed on the gate electrode.Type: ApplicationFiled: February 25, 2005Publication date: September 1, 2005Inventors: Toshiaki Komukai, Hideaki Harakawa
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Publication number: 20040159951Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.Type: ApplicationFiled: February 12, 2004Publication date: August 19, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai
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Patent number: 6727593Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.Type: GrantFiled: February 28, 2002Date of Patent: April 27, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Mitsuhiro Nakao, Masahiko Hasunuma, Hisashi Kaneko, Atsuko Sakata, Toshiaki Komukai