Patents by Inventor Toshiaki Sano
Toshiaki Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9691502Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.Type: GrantFiled: September 30, 2016Date of Patent: June 27, 2017Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Shunya Nagata, Shinji Tanaka
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Publication number: 20170117060Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.Type: ApplicationFiled: September 30, 2016Publication date: April 27, 2017Applicant: Renesas Electronics CorporationInventors: Toshiaki SANO, Shunya NAGATA, Shinji TANAKA
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Publication number: 20170092352Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: December 9, 2016Publication date: March 30, 2017Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Patent number: 9548106Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: April 21, 2016Date of Patent: January 17, 2017Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Publication number: 20160240246Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: April 21, 2016Publication date: August 18, 2016Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Publication number: 20160172022Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Inventors: Shigenobu KOMATSU, Masanao YAMAOKA, Noriaki MAEDA, Masao MORIMOTO, Yasuhisa SHIMAZAKI, Yasuyuki OKUMA, Toshiaki SANO
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Patent number: 9368194Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: April 21, 2015Date of Patent: June 14, 2016Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 9349438Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: March 14, 2015Date of Patent: May 24, 2016Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Publication number: 20150279454Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: March 14, 2015Publication date: October 1, 2015Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Publication number: 20150228330Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 9053975Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: September 18, 2014Date of Patent: June 9, 2015Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Publication number: 20150001633Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: September 18, 2014Publication date: January 1, 2015Inventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 8854869Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: August 12, 2010Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 8106449Abstract: To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.Type: GrantFiled: July 27, 2006Date of Patent: January 31, 2012Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Tomoyuki Ishii, Norifumi Kameshiro, Toshiyuki Mine
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Publication number: 20110063895Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: August 12, 2010Publication date: March 17, 2011Inventors: Shigenobu KOMATSU, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 7772053Abstract: After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.Type: GrantFiled: December 14, 2007Date of Patent: August 10, 2010Assignee: Renesas Technology Corp.Inventors: Norifumi Kameshiro, Toshiyuki Mine, Tomoyuki Ishii, Toshiaki Sano
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Publication number: 20080261357Abstract: After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.Type: ApplicationFiled: December 14, 2007Publication date: October 23, 2008Inventors: Norifumi KAMESHIRO, Toshiyuki Mine, Tomoyuki Ishii, Toshiaki Sano
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Patent number: 7375399Abstract: The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.Type: GrantFiled: June 21, 2005Date of Patent: May 20, 2008Assignee: Renesas Technology Corp.Inventors: Tomoyuki Ishii, Toshiyuki Mine, Toshiaki Sano, Norifumi Kameshiro
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Publication number: 20070063287Abstract: To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.Type: ApplicationFiled: July 27, 2006Publication date: March 22, 2007Inventors: Toshiaki Sano, Tomoyuki Ishii, Norifumi Kameshiro, Toshiyuki Mine
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Patent number: RE41868Abstract: A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations.Type: GrantFiled: February 20, 2007Date of Patent: October 26, 2010Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Toshiaki Sano, Tomoyuki Ishii, Kazuo Yano, Toshiyuki Mine