Patents by Inventor Toshiaki Yamanaka
Toshiaki Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030122159Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes;of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.Type: ApplicationFiled: November 26, 2002Publication date: July 3, 2003Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya lida, Akihiro Shimizu
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Patent number: 6576510Abstract: According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.Type: GrantFiled: April 5, 2001Date of Patent: June 10, 2003Inventors: Toshiaki Yamanaka, Shin' ichiro Kimura, Hideyuki Matsuoka, Tomonori Sekiguchi, Takeshi Sakata, Kiyoo Itoh
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Patent number: 6565455Abstract: In a multi-piece golf ball comprising a solid core, an intermediate layer, and a cover, the intermediate layer and/or the cover is formed of a heated mixture having a melt index of at least 1.0 dg/min and comprising (a) an olefin-carboxylic acid random copolymer and/or (d) a metal ion-neutralized olefin-carboxylic acid random copolymer and/or a metal ion-neutralized olefin-carboxylic acid-carboxylate random copolymer; (b) a fatty acid or derivative having a molecular weight of at least 280; and (c) a neutralizing basic inorganic metal compound. All expressed in Shore D hardness, the intermediate layer has a hardness of 40-63, the cover has a hardness of 45-68, and they satisfy the relationship: the hardness of solid core at its center≦the hardness of intermediate layer≦the hardness of cover.Type: GrantFiled: February 8, 2001Date of Patent: May 20, 2003Assignee: Bridgestone Sports Co., Ltd.Inventors: Junji Hayashi, Rinya Takesue, Toshiaki Yamanaka
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Patent number: 6565456Abstract: In a multi-piece golf ball comprising a solid core, a surrounding layer, an intermediate layer, and a cover, at least one of the surrounding layer, the intermediate layer and the cover is formed of a heated mixture having a melt index of at least 1.0 dg/min and comprising (a) an olefin-carboxylic acid-optional carboxylate random copolymer and/or (d) a metal ion-neutralized olefin-carboxylic acid-optional carboxylate random copolymer; (b) a fatty acid or derivative; and (c) a neutralizing basic inorganic metal compound. The surrounding layer, the intermediate layer and the cover have a Shore D hardness of 10-55, 40-63 and 45-68, respectively, the hardness increasing in the order of surrounding layer, intermediate layer and cover. The ball is improved in feel, control, durability and flight performance.Type: GrantFiled: February 8, 2001Date of Patent: May 20, 2003Assignee: Bridgesotne Sports Co., Ltd.Inventors: Junji Hayashi, Rinya Takesue, Toshiaki Yamanaka
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Patent number: 6548885Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: January 8, 2001Date of Patent: April 15, 2003Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20030062550Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely.Type: ApplicationFiled: October 29, 2002Publication date: April 3, 2003Applicant: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Toshihiko Tanaka, Toshiaki Yamanaka, Takeshi Sakata, Katsutaka Kimura
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Publication number: 20030054613Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.Type: ApplicationFiled: November 6, 2002Publication date: March 20, 2003Applicant: Hitachi, Ltd.Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
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Patent number: 6512245Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.Type: GrantFiled: May 17, 2001Date of Patent: January 28, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
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Patent number: 6498100Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: GrantFiled: November 30, 2001Date of Patent: December 24, 2002Assignee: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
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Publication number: 20020192902Abstract: A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line.Type: ApplicationFiled: July 29, 2002Publication date: December 19, 2002Inventors: Shinichiro Kimura, Toshiaki Yamanaka, Kiyoo Itoh, Takeshi Sakata, Tomonori Sekiguchi, Hideyuki Matsuoka
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Publication number: 20020192901Abstract: A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line.Type: ApplicationFiled: July 26, 2002Publication date: December 19, 2002Inventors: Shinichiro Kimura, Toshiaki Yamanaka, Kiyoo Itoh, Takeshi Sakata, Tomonori Sekiguchi, Hideyuki Matsuoka
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Patent number: 6495870Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.Type: GrantFiled: June 29, 1999Date of Patent: December 17, 2002Assignee: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Toshihiko Tanaka, Toshiaki Yamanaka, Takeshi Sakata, Katsutaka Kimura
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Publication number: 20020187596Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.Type: ApplicationFiled: June 6, 2002Publication date: December 12, 2002Applicant: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Akio Nishida, Yasuko Yoshida, Shuji Ikeda, Kenichi Kuroda, Shiro Kamohara, Shinichiro Kimura, Eiichi Murakami, Hideyuki Matsuoka, Masataka Minami
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Patent number: 6407420Abstract: According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.Type: GrantFiled: June 17, 1999Date of Patent: June 18, 2002Assignee: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Shin'ichiro Kimura, Hideyuki Matsuoka, Tomonori Sekiguchi, Takeshi Sakata, Kiyoo Itoh
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Publication number: 20020055261Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: ApplicationFiled: November 30, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
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Patent number: 6380085Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: GrantFiled: December 29, 2000Date of Patent: April 30, 2002Assignee: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
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Patent number: 6376304Abstract: A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed; therefore, a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied. Besides, interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, the filling up of the holes with metal and the like are unnecessary and, as a result, reliability of the process is improved.Type: GrantFiled: June 30, 2000Date of Patent: April 23, 2002Assignee: Hitachi, Ltd.Inventors: Hideyuki Matsuoka, Shinichiro Kimura, Toshiaki Yamanaka
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Publication number: 20020045360Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.Type: ApplicationFiled: August 31, 2001Publication date: April 18, 2002Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
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Publication number: 20020005534Abstract: According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.Type: ApplicationFiled: April 5, 2001Publication date: January 17, 2002Applicant: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Shin?apos;ichiro Kimura, Hideyuki Matsuoka, Tomonori Sekiguchi, Takeshi Sakata, Kiyoo Itoh
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Publication number: 20010053597Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: ApplicationFiled: December 29, 2000Publication date: December 20, 2001Applicant: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima