Abstract: A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.

Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.

Abstract: Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate.

Abstract: A comb-like or dot-like phase shifter pattern is added to a phase shifter used in phase shifting mask technology, which is then exposed onto a wafer. This enables the formation of extremely fine line patterns or space patterns having widths different from each other simultaneously. Further, when two reticles are disposed such that phase shifter patterns disposed therein intersect each other and are exposed consecutively onto a wafer, a fine hole pattern or dot pattern can be formed at a position where the phase shifter patterns intersect each other.

Abstract: In a semiconductor device and, in particular, a semiconductor memory device in which a channel region formed in a polycrystalline film of a first channel conductivity type insulated gate field effect transistor is divided into a first channel region, which is in contact with a drain region, and a second channel region and the second channel region contains a second conductivity type impurity or a first conductivity type impurity whose density is higher than the impurity density of the first channel region, the threshold voltage can be controlled and the leakage current can be made small.

Abstract: There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Abstract: A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.

Abstract: In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.

Abstract: In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L.sub.TEFF and W.sub.TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I.sub.R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I.sub.L (1.times.10.sup.-8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.

Abstract: A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor.

Abstract: A semiconductor memory device has memory cells each including first and second inverters cross-coupled to each other through first and second interconnecting conductors for forming a bistable circuit and first and second transfer gates connected between the first inverter and address signal conductors and between the second inverter and the address signal conductors, respectively. The first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on a surface of a substrate, and IG FETs constituting the first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to the parallel portions of the first and second interconnecting conductors for the cross-coupling on the surface of the substrate.

Abstract: A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped.

Abstract: A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on the substrate and are connected to the drains of the driver MOS transistors, respectively. A conductive film for fixing the sources of the driver MOS transistors to a ground voltage is formed above the principal surface of the semiconductor substrate, and this conductive film defines one electrode of a capacitance element formed on the substrate. The conductive film is formed over the load resistors formed on the semiconductor substrate so as to constitute an electric field shield for the load resistors.

Abstract: A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.

Abstract: A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate.

Abstract: Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

Abstract: A resistance element having a reduced occupied area and a high resistance which may be employed as a load resistor used in, for example, a static memory device. A high-resistance area is formed using a relatively thin film, while an interconnection area is formed using a relatively thick film, and these films are provided in such a manner that the thin film is in contact with the upper side of the thick film (the relatively thick film is a first-level film, and the relatively thin film is a second-level film).