Abstract: To transfer web contents to a web server from a computer through a network, a plurality of files composing the web contents are stored in the computer. A processor of the computer then detects files to be transferred from the plurality of files to create a transfer file list table. A transfer priority of the files to be transferred is determined by the processor on the basis of reference relation data of the files to be transferred which are designated in the transfer file list table and file format data of the plurality of files to create a transfer priority list table for the files to be transferred. The files to be transferred are transferred to the web server from a communication controller of the computer through the network by the processor in order of the transfer priority set in the transfer priority list table.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a first region having patterns formed based on grid points as intersections of grid lines; and a second region including a plurality of layout cells an outer edge of which is defined by the grid points, the layout cells having patterns formed based on a wiring rule with patterns connected to patterns of the first region among the patterns being formed based on the grid points at a boundary with the first region.

Abstract: A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.

Abstract: A memory cell has a first switching element, a second switching element and a storage capacitor and formed in an active region. A first bit line and a first word line are connected to the first switching element and a second bit line and a second word line are connected to the second switching element. A plurality of the memory cells are formed within the active region which extends in a straight line. The active region extends at an angle with respect to the bit and word lines. The active region thus has no bent portions. The deterioration of the characteristics of the memory cell caused by the bent portions can be prevented.

Abstract: A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.

Abstract: A white LED lighting device and a light source for white LED lighting that enable an energy-saving, maintenance-free operation while ensuring ample illuminance. Structure of a light source for white LED lighting, constituted by: inserting and holding a plurality of white LED elements in holding holes in a reflective plate, said plate being constituted by providing a required number of said holding holes, in a matrix-like array of prescribed pitch, in a plate of shape corresponding to the illuminating surface of a lamp body; fixing said plurality of white LED elements at locations 2 to 4 mm behind their respective electrode portions; attaching the positive and negative terminals of the white LED elements to a base plate for the LED elements, said base plate being disposed parallel to and directly behind the reflective plate; and forming, at the positive and negative terminals, a series-parallel electrical network suitable for the applied voltage.

Abstract: A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.

Abstract: A memory cell has a first switching element, a second switching element and a storage capacitor and formed in an active region. A first bit line and a first word line are connected to the first switching element and a second bit line and a second word line are connected to the second switching element. A plurality of the memory cells are formed within the active region which extends in a straight line. The active region extends at an angle with respect to the bit and word lines. The active region thus has no bent portions. The deterioration of the characteristics of the memory cell caused by the bent portions can be prevented.

Abstract: To provide a semiconductor device and a process for manufacturing the same which is capable of suppressing short channel effect and preventing a current from leaking between a contact and a silicon substrate. The semiconductor device of the present invention comprises a silicon substrate on which a source/drain area (3 in FIG. 1), a silicon oxide layer (4 in FIG. 1) and a silicon nitride layer (5 in FIG. 1) are successively formed in this order, and a trench which extend through said layers to split the source/drain area. A columnar gate electrode (9 in FIG. 1) is formed within the trench in such a manner that it is spaced from the inner wall of the trench and a lightly doped drain (LDD) area (10 in FIG. 1) is formed at an area of the bottom of the trench in which no gate electrode is disposed. In such a structure, the short channel effect which occurs in association with reduction in the gate length is suppressed.

Abstract: In order to suppress generation of waste matter which results from removing a backside film formed by growing a film on both surfaces of a semiconductor substrate and thereby attain satisfactorily high yield and productivity, on a semiconductor substrate 301, a polycrystalline silicon film 303 is formed through double-sided growth, and only on the obverse surface of the semiconductor substrate 301 a silicide film 304 is formed thereon, and then those polycrystalline silicon film 303 and silicide film 304 are worked into shape to form gate electrodes 303a. After that, on the semiconductor substrate 301, an insulating film for sidewall formation is formed to cover the gate electrodes 303a through double-sided growth, and the insulating film for sidewall formation formed on the obverse surface of the semiconductor substrate 301 is etched to form sidewall films.

Abstract: In order to suppress generation of waste matter which results from removing a backside film formed by growing a film on both surfaces of a semiconductor substrate and thereby attain satisfactorily high yield and productivity, on a semiconductor substrate 301, a polycrystalline silicon film 303 is formed through double-sided growth, and only on the obverse surface of the semiconductor substrate 301 a silicide film 304 is formed thereon, and then those polycrystalline silicon film 303 and silicide film 304 are worked into shape to form gate electrodes 303a. After that, on the semiconductor substrate 301, an insulating film for sidewall formation is formed to cover the gate electrodes 303a through double-sided growth, and the insulating film for sidewall formation formed on the obverse surface of the semiconductor substrate 301 is etched to form sidewall films.

Abstract: A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle &thgr; on the active region. The boundary between the element-isolating region and the active region intersects the gate electrode so that the line segments of the boundary at which said intersection takes place, are approximately parallel to the bisector of the bent-angle &thgr; of the bent portion of the gate electrode. In this semiconductor device, the variation in width of gate electrode is small and accordingly the variation in properties is small, even when the relative position of gate electrode and active region of MOSFET has shifted slightly.

Abstract: The method of forming device isolation structures in semiconductor devices, according to the present invention, is comprised of a barrier layer formation step of forming predetermined isolation trenches on the primary surface of the semiconductor substrate, next oxidizing the surface of these isolation trenches so as to form an oxidized layer, and then depositing a oxidation stopping layer on top; an isolation trench filling step of depositing insulating material to the entire surface of the primary substrate surface so as to fill in the isolation trenches after the barrier layer formation step; and an annealing step of performing a wet oxidation process at a temperature higher than any of the processes after the isolation trench filling step forming the semiconductor device.

Abstract: A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle &thgr; on the active region. The boundary between the element-isolating region and the active region intersects the gate electrode so that the line segments of the boundary at which said intersection takes place, are approximately parallel to the bisector of the bent-angle &thgr; of the bent portion of the gate electrode. In this semiconductor device, the variation in width of gate electrode is small and accordingly the variation in properties is small, even when the relative position of gate electrode and active region of MOSFET has shifted slightly.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of forming a silicon oxide film on a semiconductor substrate for defining device isolation regions therewith, forming a gate oxide film over the product resulting from the previous step, forming an electrically conductive film over the product resulting from the previous step, forming a first insulating film over the electrically conductive film, etching the first insulating film and the electrically conductive film to thereby form a first wiring layer comprising a plurality of sections, forming a second insulating film around a sidewall of the sections of the first wiring layer, forming a first interlayer insulating film over the product resulting from the previous step, simultaneously forming a first contact hole reaching the semiconductor substrate and a second contact hole reaching the first wiring layer, forming a second wiring layer over the product resulting from the previous step, forming a second interlayer insulati

Abstract: A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle &thgr; on the active region. The boundary between the element-isolating region and the active region intersects the gate electrode so that the line segments of the boundary at which said intersection takes place, are approximately parallel to the bisector of the bent-angle &thgr; of the bent portion of the gate electrode. In this semiconductor device, the variation in width of gate electrode is small and accordingly the variation in properties is small, even when the relative position of gate electrode and active region of MOSFET has shifted slightly.

Abstract: In a resistance element formed by a connection layer including a flexing portion, the connection layer is constructed by a high resistance section including the flexing portion and a low resistance section. Boundaries between the high resistance section and the low resistance section are approximately in parallel with a bisector of the connection layer at the flexing portion.

Abstract: In a method of manufacturing a semiconductor device, laminate structures with a first insulating film as a top film are formed on a semiconductor region having a first conductive type. One of the laminate structures is a gate electrode structure including a second insulating film as a gate insulating film formed on the semiconductor region, a conductive layer as a gate electrode formed on the gate insulating film, and the first insulating film formed on the gate electrode. Next, side wall insulating films are formed on side walls of the gate electrode structure and laminate structures adjacent to the gate electrode structure. Ion implantation of impurity of a second conductive type different from the first conductive type is executed using the side wall insulating films in a self-alignment manner to produce the source/drain regions for a metal-oxide-semiconductor (MOS) transistor.

Abstract: A semiconductor memory device capable of high-speed operation, low-voltage operation, and low power-consumption. First and second driver transistors are laid out in such a way that the channel regions of first and second driver transistors extend in a direction oblique to first and second word lines. First and second transfer transistors are laid out in such a way that the channel regions of the first and second transfer transistors extend in a direction perpendicular to the first and second word lines. The channel regions of the first and second transfer transistors and the contact resistance of the first and second bit contacts are substantially constant independent of an allowable overlay error, respectively, thereby keeping the capability of the first and second transfer transistors and the bit contact resistance the same independent of the allowable overlay error.