Patents by Inventor Toshiharu NAGUMO
Toshiharu NAGUMO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Semiconductor memory device including memory pillars and transistor and manufacturing method thereof
Patent number: 10896913Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate. The semiconductor substrate includes a first surface. A first semiconductor layer is provided on a first region of the first surface. A first transistor is provided on the first semiconductor layer. A second semiconductor layer is provided on a second region of the first surface. A second transistor is provided on the second semiconductor layer. A stacked body is provided on a third region of the first surface. The stacked body includes a plurality of conductors and a plurality of memory pillars. A first insulator is provided between the first semiconductor layer and the second semiconductor layer.Type: GrantFiled: March 11, 2019Date of Patent: January 19, 2021Assignee: Toshiba Memory CorporationInventors: Takashi Fukushima, Junya Fujita, Toshiharu Nagumo -
Publication number: 20200083243Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate. The semiconductor substrate includes a first surface. A first semiconductor layer is provided on a first region of the first surface. A first transistor is provided on the first semiconductor layer. A second semiconductor layer is provided on a second region of the first surface. A second transistor is provided on the second semiconductor layer. A stacked body is provided on a third region of the first surface. The stacked body includes a plurality of conductors and a plurality of memory pillars. A first insulator is provided between the first semiconductor layer and the second semiconductor layer.Type: ApplicationFiled: March 11, 2019Publication date: March 12, 2020Applicant: Toshiba Memory CorporationInventors: Takashi FUKUSHIMA, Junya FUJITA, Toshiharu NAGUMO
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Publication number: 20180301552Abstract: A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.Type: ApplicationFiled: June 14, 2018Publication date: October 18, 2018Inventor: Toshiharu NAGUMO
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Patent number: 10069010Abstract: A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.Type: GrantFiled: February 25, 2014Date of Patent: September 4, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Toshiharu Nagumo
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Patent number: 10020399Abstract: A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.Type: GrantFiled: February 25, 2014Date of Patent: July 10, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Toshiharu Nagumo
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Patent number: 9929177Abstract: A semiconductor memory device includes a first semiconductor layer; a stacked body including a plurality of electrode layers stacked in a first direction; a metal layer provided in the first direction between the first semiconductor layer and the stacked body; a second semiconductor layer extending in the first direction through the stacked body and the metal layer, and being electrically connected to the first semiconductor layer.Type: GrantFiled: January 12, 2017Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Toshiharu Nagumo
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Publication number: 20170309638Abstract: A semiconductor memory device includes a first semiconductor layer; a stacked body including a plurality of electrode layers stacked in a first direction; a metal layer provided in the first direction between the first semiconductor layer and the stacked body; a second semiconductor layer extending in the first direction through the stacked body and the metal layer, and being electrically connected to the first semiconductor layer.Type: ApplicationFiled: January 12, 2017Publication date: October 26, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Toshiharu NAGUMO
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Patent number: 9589951Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. Each of the source region and the drain region is in contact with the semiconductor layer.Type: GrantFiled: August 17, 2015Date of Patent: March 7, 2017Assignee: Renesas Electronics CorporationInventors: Toshiharu Nagumo, Takashi Hase, Kiyoshi Takeuchi, Ippei Kume
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Patent number: 9564486Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.Type: GrantFiled: August 28, 2015Date of Patent: February 7, 2017Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATIONInventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
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Patent number: 9553131Abstract: Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PL2 is a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BL2 is 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.Type: GrantFiled: July 24, 2015Date of Patent: January 24, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshiharu Nagumo, Kiyoshi Takeuchi, Toyoji Yamamoto
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Patent number: 9362308Abstract: A semiconductor device and method making it comprises pFETs with an SiGe channel and nFETs with an Si channel, formed on an SOI substrate. Improved uniformity of fin height and width is attained by forming the fins additively by depositing an SiGe layer on the SOI substrate and forming first fins from the superposed SiGe layer and underlying thin Si film of the SOI substrate. Second fins of Si can then be formed by replacing the upper SiGe portions of selected first fins with Si.Type: GrantFiled: March 11, 2014Date of Patent: June 7, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Toshiharu Nagumo
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Patent number: 9324790Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.Type: GrantFiled: November 19, 2013Date of Patent: April 26, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION, GLOBALFOUNDRIES INC.Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
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Patent number: 9305846Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.Type: GrantFiled: January 19, 2015Date of Patent: April 5, 2016Assignees: GlobalFoundries Inc., International Business Machines Corporation, Renesas Electronics CorporationInventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Steven Bentley, Toshiharu Nagumo, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz
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Publication number: 20160079426Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Inventors: Ippei KUME, Hiroshi TAKEDA, Toshiharu NAGUMO, Takashi HASE
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Publication number: 20160056207Abstract: Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PL2 is a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BL2 is 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.Type: ApplicationFiled: July 24, 2015Publication date: February 25, 2016Inventors: Toshiharu NAGUMO, Kiyoshi TAKEUCHI, Toyoji YAMAMOTO
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Publication number: 20160056145Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. Each of the source region and the drain region is in contact with the semiconductor layer.Type: ApplicationFiled: August 17, 2015Publication date: February 25, 2016Inventors: Toshiharu Nagumo, Takashi Hase, Kiyoshi Takeuchi, Ippei Kume
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Publication number: 20160035728Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Ajey Poovannummoottil Jacob, Steven John Bentley, Murat Kerem Akarvardar, Jody Alan Fronheiser, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Toshiharu Nagumo
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Publication number: 20160027872Abstract: A semiconductor device, includes a substrate, a source structure and a drain structure formed on the substrate. At least one interconnect structure interconnects the source structure and the drain structure and serves as a channel therebetween. A gate structure is formed over the at least one interconnect structure to provide a control of a conductivity of carriers in the channel. Each of the interconnect structures include a center core serving as a backbias electrode for the channel.Type: ApplicationFiled: October 2, 2015Publication date: January 28, 2016Inventors: Tomohiro HIRAI, Toshiharu NAGUMO
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Publication number: 20160020312Abstract: A method of fabricating a semiconductor device with a reduced leakage method includes forming a channel structure on a substrate, the channel structure having a non-uniform composition, in a cross-sectional view, that comprises a core region and a peripheral region. An etch rate of the core region differs from an etch rate of the peripheral region. A source structure connected to one end of the channel structure is formed, and a drain structure connected to the other end of the channel structure is formed. At least a portion of the core region is electively etched and a gate structure to cover at least a portion of a surface of the channel structure, is formed, the gate structure comprising a film of insulation material and a gate electrode.Type: ApplicationFiled: September 30, 2015Publication date: January 21, 2016Inventors: Tomohiro HIRAI, Shogo Mochizuki, Toshiharu Nagumo
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Semiconductor device with group-III nitride compound semiconductor layer on substrate for transistor
Patent number: 9231105Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.Type: GrantFiled: August 21, 2014Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Hiroshi Takeda, Toshiharu Nagumo, Takashi Hase