Abstract: A light control device includes a GH cell and a polarizer wherein a host material is made of a negative type liquid crystal whose dielectric anisotropy is negative and a guest material is made of a dichromatic positive type dye. The polarizer is provided at a side of light incident on the polarizer. A cell gap ranges from 2 &mgr;m to 4 &mgr;m, at least, in an effective light path.

Abstract: A light control device comprises a liquid crystal cell 12, and a pulse control unit 62 or 64 wherein when a transmittance of light transmitted from said liquid crystal element is changed from an actual light transmittance to an intended light transmittance, the pulse control unit is able to insert beforehand a drive pulse for control corresponding to a minimum light transmittance or a maximum light transmittance, at least, prior to application of a drive pulse corresponding to the intended light transmittance. A method of driving the light control device is also described wherein the light control device is driven by use of the drive pulse for control, along with a pickup device wherein the light control device is arranged in a light path of a pickup system.

Abstract: A light control device and an imaging device suitable for the effective and stabilized driving of a Guest-Host type liquid crystal element. A light control device (23) which is provided with a light controlling GH cell (12) and a UV cut filter (65) provided on the light incident side of the GH cell (12), and which is therefore reduced significantly in the quantity of ultraviolet ray applied to the GH cell (12), thereby preventing the photodecompositon or photodegradation of materials constituting a liquid crystal layer in the GH cell (12); and an imaging device such as a CCD camera (50) having this light control device disposed on the optical path thereof.

Abstract: The present invention relates to an electrical dimmer device and its driving method applicable to, for example, an image pickup unit and a display unit. In the present invention, when a control signal for stop adjustment is changed from its current value of stop adjustment (±VX1) to a larger value (±VY1) (when the light transmissivity of a positive type liquid crystal is raised, or when the light transmissivity of a negative type liquid crystal is lowered), the control signal is temporarily varied to an intermediate value (±VZ1) which is still larger than the larger value (±VY1). The energy of the still larger value (±VZ1) and a time during which that varied value is applied are determined in accordance with predetermined values. By doing so, it is possible to make a response speed when changing the light transmissivity extremely faster and thus attain a response time of, e.g. one field period of time or less required for a stop mechanism of video camera.

Abstract: An adhesion layer made from Al film or Ti film is formed on Cu electrode pad portions as external connection terminals of a Cu interconnection layer of an LSI formed on the surface layer of a semiconductor substrate. A BLM film having a stacked structure of Cr/Cu/Au or Ti/Cu/Au is formed on the adhesion layer. Solder ball bumps made from Pb and Sn are formed on the BLM film. The adhesion layer ensures a high adhesion strength and a high electric contact characteristic between the Cu electrode pad portions and the BLM film, that is, between the Cu electrode pads and the solder ball bumps.

Abstract: There is provided a semiconductor device having a semiconductor chip in which a first protrusion electrode is formed on the semiconductor substrate; and an intermediate substrate which comprises a base substrate, a first external terminal provided in said base substrate, which is joined to said first protrusion electrode, a second external terminal provided in said base substrate, an electrode section being exposed on both surfaces of said base substrate, and a second protrusion electrode formed at one end face of said second external terminal, a plurality of said intermediate substrates being stacked in layers by joining said second protrusion electrode to the other end face of said second external terminal, thus enabling miniaturizing and lightening electronic equipment and realizing high reliability and high performance.

Abstract: An electronic circuit device of a three-dimensional mounting mode capable of being produced by a simple method while suppressing the production costs and of a structure resistant to external stress, including first-mounting-board wiring portions formed on a first mounting board, first mounting parts mounted on the first mounting board, bumps formed on the first mounting board connecting to the first-mounting-board wiring portion, a protective layer formed covering the first mounting parts so that at least the portions near the tops of the bumps are exposed, a second mounting board stacked as an upper layer of the protective layer, second-mounting-board wiring portions formed on the second mounting board in order to connect to the bumps, and second mounting parts mounted connecting to the second-mounting-board wiring portions on the second mounting board at the surface of the second mounting board opposite to the protective layer side, and a method of production of the same.

Abstract: A method of manufacturing a semiconductor device, comprising preparing a semiconductor device wafer which is formed with an LSI; working the semiconductor device wafer from the back surface thereof, thereby to diminish the thickness of the semiconductor device wafer to at most 200 [&mgr;m]; forming penetrant apertures in the resulting semiconductor device wafer; forming wiring plugs (23 in FIG. 7) in the respective penetrant apertures; dicing the semiconductor device wafer, thereby to be divided into semiconductor chips (7) each of which includes the wiring plugs (23); and mounting at least two of the semiconductor chips (7) over a printed-wiring circuit board (25) through bumps (10) connected with the wiring plugs (23). Thus, the ultrathin stacked multilevel mounting of semiconductor device components can be realized at a high reliability and with a high functionality.

Abstract: A preprocessing method of a metal film formation process before formation of a BLM film on a resist film of a substrate to be processed, wherein the resist film of substrate to be processed is irradiated with plasma, utilizing a plasma processing apparatus providing independent plasma generating power source and substrate bias power source to form an overhand area at the end face of a connecting hole and change the property of the surface area.

Abstract: A light control device includes a GH cell and a polarizer wherein a host material is made of a negative type liquid crystal whose dielectric anisotropy is negative and a guest material is made of a dichromatic positive type dye. The polarizer is provided at a side of light incident on the polarizer. A cell gap ranges from 2 &mgr;m to 4 &mgr;m, at least, in an effective light path.

Abstract: A light control device comprises a liquid crystal cell 12, and a pulse control unit 62 or 64 wherein when a transmittance of light transmitted from said liquid crystal element is changed from an actual light transmittance to an intended light transmittance, the pulse control unit is able to insert beforehand a drive pulse for control corresponding to a minimum light transmittance or a maximum light transmittance, at least, prior to application of a drive pulse corresponding to the intended light transmittance. A method of driving the light control device is also described wherein the light control device is driven by use of the drive pulse for control, along with a pickup device wherein the light control device is arranged in a light path of a pickup system.

Abstract: A method of manufacturing a semiconductor device, comprising preparing a semiconductor device wafer which is formed with an LSI; working the semiconductor device wafer from the back surface thereof, thereby to diminish the thickness of the semiconductor device wafer to at most 200 [&mgr;m]; forming penetrant apertures in the resulting semiconductor device wafer; forming wiring plugs (23 in FIG. 7) in the respective penetrant apertures; dicing the semiconductor device wafer, thereby to be divided into semiconductor chips (7) each of which includes the wiring plugs (23); and mounting at least two of the semiconductor chips (7) over a printed-wiring circuit board (25) through bumps (10) connected with the wiring plugs (23). Thus, the ultrathin stacked multilevel mounting of semiconductor device components can be realized at a high reliability and with a high functionality.

Abstract: A semiconductor device is characterized by mixedly mount a logic chip, an analog chip, a memory chip, etc. by stacking them while stabilizing power supply lines and ground lines of each chip. The semiconductor device has an intermediate substrate having a conductive portion and also having, on its one surface, an external connection terminal conducted to the conductive portion; and semiconductor chips each of which has connection portions, and which are mounted on both the surfaces of the intermediate substrate. At least two of the above semiconductor chips are electrically conducted to each other via the conductive portion of the intermediate substrate. At least one of a power supply line, a ground line, and a signal line of each of the semiconductor chips is connected to the conductive portion of the intermediate substrate via two or more, conducted to each other, of the connection portions.

Abstract: There are provided a base member 14, a position restriction mechanism 15, a height restriction mechanism 17, an evenness holding mechanism, and an alignment mechanism 20, 22. A plurality of semiconductor modules is serially layered on the base member. Each semiconductor module comprises a semiconductor chip 7 mounted on a printed-wiring board 6 and a bump 13 formed on an interlayer connection land 8. The position restriction mechanism 15 restricts respective positions of the semiconductor modules 2 to be layered on the base member 14. The height restriction mechanism 17 restricts the height of the entire layered semiconductor module unit 4 layered on the base member 14. The evenness holding mechanism maintains evenness of the semiconductor module 2. The alignment mechanism 20, 22 aligns a mother substrate 5 on which a multilayer semiconductor module unit 4 is mounted.

Abstract: An adhesion layer made from Al film or Ti film is formed on Cu electrode pad portions as external connection terminals of a Cu interconnection layer of an LSI formed on the surface layer of a semiconductor substrate. A BLM film having a stacked structure of Cr/Cu/Au or Ti/Cu/Au is formed on the adhesion layer. Solder ball bumps made from Pb and Sn are formed on the BLM film. The adhesion layer ensures a high adhesion strength and a high electric contact characteristic between the Cu electrode pad portions and the BLM film, that is, between the Cu electrode pads and the solder ball bumps.

Abstract: A process of production of a semiconductor apparatus which can suppress a rise in the electrical resistance and a decline in the joint strength at the bump connection interfaces and improve the connection reliability when using the method of reinforcing the bases of the bumps by a resin film. Bumps are formed on a semiconductor wafer formed with a pattern circuit of a semiconductor chip so as to connect to the circuit pattern, a resin film is formed on the bump forming surface of the semiconductor wafer to a thickness giving a surface lower than the height of the bumps while sealing the spaces between the bumps, plasma cleaning etc., is used to remove the sealing resin components deposited on the surface portions of the bumps or natural oxides or other insulating impurities to clean and activate the surfaces of the bumps, and the chip is mounted on a mounting board.

Abstract: Prior to cleaning spontaneous oxide films formed on the surface of an impurity diffusion layer or a lower layer wiring exposed at the bottom of a contact hole by sputtering by discharge plasmas with a rare gas, a dummy substrate formed with an insulation film is sputtered to deposit an insulation film on the inner wall of a plasma processing apparatus. Plasma ashing for the inner wall of the plasma processing apparatus may be used together. In this case, cleaning at higher accuracy is possible by monitoring the insulation resistance value at the inner wall of the plasma processing apparatus. Plasma processing is stabilized by always keeping the insulation resistance value high for the inner wall of the plasma processing chamber. Interconnection with low resistivity and high reliability can be attained by a fine contact hole of high aspect ratio.

Abstract: Disclosed is a bump designed to certainly moderate a thermal stress applied between a semiconductor device and a printed circuit board and enhance the strength of a bonding portion without use of a sealing resin, and a method of manufacturing the bump. The bump includes a relatively elastic first ball bump formed on an electrode pad provided on a semiconductor device; and a second ball bump formed in such a manner as to be overlapped on the first ball bump at least in the direction perpendicular to the electrode pad. The second ball bump is different in material or composition from the first ball bump and is adapted to be in contact with an eutectic solder pre-coated on a connection land of a printed circuit board.

Abstract: A refractory metal layer is formed on the entire surface of an interlayer insulating film having a connection hole, and then etched back by using an etching gas containing at least one of Kr, Xe, and Rn, each of which is an inert gas element having a large atomic weight. A contact plug is formed by using a resulting refractory metal layer. By employing this manufacturing method, a refractory metal layer formed by the blanket CVD method can be etched while the loading effect is prevented during overetching, and a contact plug having a flat burying surface can be formed without causing any abnormal eroded portion in a connection hole of an interlayer insulating film.

Abstract: A preprocessing method of a metal film formation process before formation of a BLM film on a resist film of a substrate to be processed, wherein the resist film of substrate to be processed is irradiated with plasma, utilizing a plasma processing apparatus providing independent plasma generating power source and substrate bias power source to form an overhand area at the end face of a connecting hole and change the property of the surface area. The plasma generating power and substrate bias voltage can be set adequately. Thereby irradiation of plasma can be performed easily, change of property at the surface of resist film can be done quickly and shape control of the end face of the connecting hole can also be executed very easily.