Patents by Inventor Toshihide Ito

Toshihide Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072119
    Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, a first member, a first layer, and a second layer. The silicon carbide member includes a first region. The first member includes silicon and oxygen. The first layer is provided between the first region and the first member. The first layer includes a bond between silicon and nitrogen. The second layer is provided between the first layer and the first member. The second layer includes a bond between silicon and oxygen and a bond between silicon and nitrogen.
    Type: Application
    Filed: February 16, 2023
    Publication date: February 29, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio NAKABAYASHI, Tatsuo SHIMIZU, Toshihide ITO, Chiharu OTA, Johji NISHIO
  • Patent number: 11848211
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 19, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Publication number: 20230387216
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3, and a carbon concentration at the position is equal to or less than 1×1018 cm?3.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 30, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
  • Patent number: 11764269
    Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: September 19, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Patent number: 11764270
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3, and a carbon concentration at the position is equal to or less than 1×1018 cm?3.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: September 19, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Publication number: 20230207321
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 1021 cm-3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1 × 1018 cm-3 and a carbon concentration at the first position is equal to or less than 1 × 1018 cm-3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1 × 1018 cm-3.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 29, 2023
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
  • Publication number: 20230197790
    Abstract: A method for manufacturing a semiconductor device of an embodiment includes performing first ion implantation of implanting aluminum (Al) into a silicon carbide layer in a first projected range and a first dose amount, performing second ion implantation of implanting carbon (C) into the silicon carbide layer in a second projected range and a second dose amount which is a dose amount equal to or more than 10 times the first dose amount, performing a first heat treatment of 1600° C. or more, performing an oxidation treatment of oxidizing the silicon carbide layer, performing an etching process of etching the silicon carbide layer in an atmosphere containing a hydrogen gas, forming a silicon oxide film on the silicon carbide layer, and forming a gate electrode on the silicon oxide film.
    Type: Application
    Filed: August 30, 2022
    Publication date: June 22, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Toshihide ITO, Chiharu OTA, Johji NISHIO
  • Patent number: 11621167
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: April 4, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Publication number: 20230084127
    Abstract: A semiconductor device manufacturing method of embodiments includes: forming a silicon oxide film on a surface of a silicon carbide layer; performing a first heat treatment in an atmosphere containing nitrogen gas at a temperature equal to or more than 1200° C. and equal to or less than 1600° C.; and performing a second heat treatment in an atmosphere containing nitrogen oxide gas at a temperature equal to or more than 750° C. and equal to or less than 1050° C.
    Type: Application
    Filed: March 7, 2022
    Publication date: March 16, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Toshihide ITO, Chiharu OTA, Shigeto FUKATSU, Johji NISHIO, Ryosuke IIJIMA
  • Publication number: 20220416030
    Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 29, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
  • Patent number: 11469301
    Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: October 11, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Patent number: 11424326
    Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: August 23, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio Nakabayashi, Tatsuo Shimizu, Toshihide Ito, Chiharu Ota, Johji Nishio
  • Publication number: 20220130673
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Patent number: 11239079
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: February 1, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Publication number: 20220005925
    Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018cm?3.
    Type: Application
    Filed: February 16, 2021
    Publication date: January 6, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
  • Publication number: 20210367040
    Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.
    Type: Application
    Filed: January 26, 2021
    Publication date: November 25, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio NAKABAYASHI, Tatsuo SHIMIZU, Toshihide ITO, Chiharu OTA, Johji NISHIO
  • Publication number: 20210296446
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3, and a carbon concentration at the position is equal to or less than 1×1018 cm?3.
    Type: Application
    Filed: August 13, 2020
    Publication date: September 23, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Publication number: 20210296128
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.
    Type: Application
    Filed: August 24, 2020
    Publication date: September 23, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
  • Patent number: 10741395
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing a first heat treatment of a first film at a first temperature not less than 500° C. and not more than 900° C. in a first atmosphere including oxygen. The first film includes silicon and oxygen and is deposited on a semiconductor member including silicon carbide. The method can include performing, after the first heat treatment, a second heat treatment of the first film at a second temperature not less than 1200° C. but less than 1400° C. in a second atmosphere including nitrogen.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: August 11, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Asaba, Ryosuke Iijima, Yukio Nakabayashi, Shigeto Fukatsu, Toshihide Ito
  • Patent number: 10714610
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima, Toshihide Ito, Shunsuke Asaba, Yukio Nakabayashi, Shigeto Fukatsu