Patents by Inventor Toshihide Ito

Toshihide Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080236122
    Abstract: A honeycomb structure including plural cells with holes arranged in a longitudinal direction, a peripheral wall, and a defective portion formed on the peripheral wall that is mended with a mending material that is in a color different from the color of the peripheral wall. Also, a method is provided for manufacturing a honeycomb structure including plural cells with holes arranged in a longitudinal direction and a peripheral wall which method involves mending a defective portion formed on the peripheral wall of the honeycomb structure with a mending material in a color different from the color of the peripheral wall.
    Type: Application
    Filed: October 26, 2007
    Publication date: October 2, 2008
    Applicant: IBIDEN CO., LTD.
    Inventor: Toshihide ITO
  • Publication number: 20080173927
    Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.
    Type: Application
    Filed: September 6, 2007
    Publication date: July 24, 2008
    Inventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
  • Patent number: 7372546
    Abstract: In order to adjust the optical axis of a light beam L1 in an exposure apparatus, on a support body in an XYZ three-dimensional coordinate system are mounted: a first mirror 10 having a reflective surface M1 obtained by rotating a plane parallel to the XY plane around an axis 11 parallel to the Y axis by an angle of ?; and a second mirror 20 having a reflective surface M2 obtained by rotating a plane parallel to the XZ plane around an axis 21 parallel to the X axis by an angle of ?. There are provided: position adjustment means for moving the entire support body having the two mirrors parallel to the XY plane; and angle adjustment means for adjusting the angle of the second mirror 20. The incident light L1 is reflected on the reflective surfaces M1 and M2 to be output as an outgoing light L3, where it is possible to perform an optical axis adjustment concerning position and angle by controlling the position adjustment means and the angle adjustment means.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: May 13, 2008
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yoshinori Tabata, Toshihide Ito, Takeshi Kawakami, Tsuyoshi Kashiwagi, Tsuyoshi Yamauchi
  • Patent number: 7303978
    Abstract: To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: December 4, 2007
    Assignee: NEC Toppan Circuit Solutions, Inc.
    Inventor: Toshihide Ito
  • Publication number: 20060072092
    Abstract: In order to adjust the optical axis of a light beam L1 in an exposure apparatus, on a support body in an XYZ three-dimensional coordinate system are mounted: a first mirror 10 having a reflective surface M1 obtained by rotating a plane parallel to the XY plane around an axis 11 parallel to the Y axis by an angle of ?; and a second mirror 20 having a reflective surface M2 obtained by rotating a plane parallel to the XZ plane around an axis 21 parallel to the X axis by an angle of ?. There are provided: position adjustment means for moving the entire support body having the two mirrors parallel to the XY plane; and angle adjustment means for adjusting the angle of the second mirror 20. The incident light L1 is reflected on the reflective surfaces M1 and M2 to be output as an outgoing light L3, where it is possible to perform an optical axis adjustment concerning position and angle by controlling the position adjustment means and the angle adjustment means.
    Type: Application
    Filed: May 12, 2005
    Publication date: April 6, 2006
    Inventors: Yoshinori Tabata, Toshihide Ito, Takeshi Kawakami, Tsuyoshi Kashiwagi, Tsuyoshi Yamauchi
  • Patent number: 6938336
    Abstract: A resin filled board is manufactured by forming roughened surfaces on a conductive layer in a throughhole before it is filled with a resin, forming smooth surfaces on conductive layers on the top and bottom of the board, printing the resin using a mask having an opening at a position corresponding to the throughhole to selectively fill the resin in the throughhole, and curing the resin. In this way, the surface of the conductive layer around the throughhole is smoothed, so that hardly any of the resin remains on the surfaces near the throughhole when the surfaces of the board is mechanically polished after the resin is cured. Also, the filling resin will not fall down into the throughhole.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: September 6, 2005
    Assignee: NEC Toppan Circuit Solutions, Inc.
    Inventors: Toshihide Ito, Satoshi Nakamura
  • Publication number: 20050156326
    Abstract: To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads.
    Type: Application
    Filed: January 6, 2005
    Publication date: July 21, 2005
    Applicant: NEC Toppan Circuit Solutions, Inc.
    Inventor: Toshihide Ito
  • Publication number: 20040247467
    Abstract: To make a Wesco type fuel pump to supply pressure-increased fuel toward a fuel injection valve with no time delay at a time of restarting an engine with an excellent restarting property, an impeller (8) which is rotated by an electric motor (M) arranged within a motor chamber (9) is arranged within a pump chamber (7), a fuel inflow passage (6) which communicates with the outside and a discharge hole (5) which communicates with the motor chamber (9) are open to the pump chamber (7), and the discharge hole (5) is provided with a fuel holding function which inhibits air from flowing into the motor chamber (9) from the pump chamber (7) at a time when the engine stops.
    Type: Application
    Filed: March 25, 2004
    Publication date: December 9, 2004
    Inventors: Toshihide Ito, Toshihiro Arai, Michiru Fukuda
  • Patent number: 6702176
    Abstract: A solder consists essentially of 1.0% to 4.0% of Ag by mass, 0.2% to 1.3% of Cu by mass, 0.02% to 0.06% of Co by mass, and the remaining of Sn and inevitable impurities.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: March 9, 2004
    Assignees: NEC Toppan Circuit Solutions, INC, Solder Coat Co., Ltd.
    Inventors: Toshihide Ito, Shiro Hara
  • Publication number: 20030155638
    Abstract: To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads.
    Type: Application
    Filed: January 24, 2003
    Publication date: August 21, 2003
    Applicant: NEC Toppan Circuit Solutions, Inc.
    Inventor: Toshihide Ito
  • Publication number: 20030074790
    Abstract: A resin filled board is manufactured by forming roughened surfaces on a conductive layer in a throughhole before it is filled with a resin, forming smooth surfaces on conductive layers on the top and bottom of the board, printing the resin using a mask having an opening at a position corresponding to the throughhole to selectively fill the resin in the throughhole, and curing the resin. In this way, the surface of the conductive layer around the throughhole is smoothed, so that hardly any of the resin remains on the surfaces near the throughhole when the surfaces of the board is mechanically polished after the resin is cured. Also, the filling resin will not fall down into the throughhole.
    Type: Application
    Filed: October 18, 2002
    Publication date: April 24, 2003
    Applicant: NEC Toppan Circuit Solutions, Inc.
    Inventors: Toshihide Ito, Satoshi Nakamura
  • Publication number: 20020159913
    Abstract: A Pb-free solder is provided, which has a satisfactory low melting point and suppresses effectively the “copper leaching” phenomenon. The solder is difficult to be oxidized and has a high wettability. The solder consists essentially of (a) 1.0 to 4.0 wt % of Ag, (b) 0.4 to 1.3 wt % of Cu; (c) at least one of 0.02 to 0.06 wt % (or 0.02 to 0.04 wt %) of Ni and 0.02 to 0.06 wt % (or 0.02 to 0.05 wt %) of Fe; and (d) a balance of Sn. The solder has a copper dissolution rate of 0.20 or 0.15 &mgr;m or less. Preferably, the solder has a liquidus temperature of 240° C. or lower, in which a satisfactory low melting point is ensured. More preferably, the solder has a liquidus temperature of 230° C. or lower. It is preferred that the solder has a viscosity of 2.5 cP or lower.
    Type: Application
    Filed: April 23, 2002
    Publication date: October 31, 2002
    Inventors: Toshihide Ito, Shiro Hara
  • Publication number: 20020117539
    Abstract: A solder consists essentially of 1.0% to 4.0% of Ag by mass, 0.2% to 1.3% of Cu by mass, 0.02% to 0.06% of Co by mass, and the remaining of Sn and inevitable impurities.
    Type: Application
    Filed: December 11, 2001
    Publication date: August 29, 2002
    Applicant: NEC CORPORATION
    Inventors: Toshihide Ito, Shiro Hara