Patents by Inventor Toshihiko Akiba
Toshihiko Akiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411368Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a wiring substrate, a semiconductor chip and a capacitor mounted on the upper surface of the wiring substrate, and a lid formed of a metallic plate covering the semiconductor chip and the wire in substrate. The semiconductor chip is bonded to the lid via a conductive adhesive layer, and the capacitor, which is thicker than the thickness of the semiconductor chip, is disposed in the cut off portion provided in the lid, and is exposed from the lid.Type: ApplicationFiled: September 6, 2023Publication date: December 21, 2023Inventors: Toshihiko AKIBA, Kenji SAKATA, Nobuhiro KINOSHITA, Yosuke KATSURA
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Patent number: 11784173Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.Type: GrantFiled: September 27, 2021Date of Patent: October 10, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshihiko Akiba, Kenji Sakata, Nobuhiro Kinoshita, Yosuke Katsura
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Publication number: 20220165638Abstract: A semiconductor device includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat release sheet arranged on the semiconductor chip to cover the entire semiconductor chip and having a larger area than an area of the semiconductor chip; and a cover member which covers the semiconductor chip and the heat release sheet and to which the heat release sheet is fixed. The cover member has a first portion facing the semiconductor chip, a flange portion arranged in a periphery of the first portion and bonded and fixed onto the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member viewed from the heat release sheet, the heat release sheet is bonded/fixed to the cover member through a bonding member partially arranged between the heat release sheet and the cover member.Type: ApplicationFiled: November 3, 2021Publication date: May 26, 2022Inventors: Toshihiko AKIBA, Yusuke TANUMA
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Publication number: 20220013508Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Inventors: Toshihiko AKIBA, Kenji SAKATA, Nobuhiro KINOSHITA, Yosuke KATSURA
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Patent number: 11171547Abstract: One aspect of an electric actuator of the disclosure includes: a motor having a motor shaft rotating about a central axis; a speed reduction mechanism connected to a portion on one side in an axial direction of the motor shaft; a case accommodating the motor and the speed reduction mechanism; an output part to which rotation of the motor shaft is transmitted via the speed reduction mechanism; a rotation detector having a rotation sensor detecting rotation of the output part; and a wiring member electrically connected with the rotation sensor. The case has a first concave part located on an outer surface of the case. One end part of the wiring member penetrates the case from inside the case and protrudes inside the first concave part. The rotation sensor is located inside the first concave part and connected with one end part of the wiring member.Type: GrantFiled: June 14, 2019Date of Patent: November 9, 2021Assignee: NIDEC TOSOK CORPORATIONInventors: Hiroshi Shirai, Yutaka Uematsu, Kazuhiro Saito, Shuichi Kinjo, Toshihiko Akiba, Koichi Ishige
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Patent number: 11158617Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.Type: GrantFiled: June 18, 2019Date of Patent: October 26, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshihiko Akiba, Kenji Sakata, Nobuhiro Kinoshita, Yosuke Katsura
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Patent number: 11063009Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.Type: GrantFiled: February 5, 2018Date of Patent: July 13, 2021Assignee: Renesas Electronics CorporationInventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
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Patent number: 10566255Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: July 23, 2019Date of Patent: February 18, 2020Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20200006303Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.Type: ApplicationFiled: June 18, 2019Publication date: January 2, 2020Inventors: Toshihiko AKIBA, Kenji SAKATA, Nobuhiro KINOSHITA, Yosuke KATSURA
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Publication number: 20200007010Abstract: One aspect of an electric actuator of the disclosure includes: a motor having a motor shaft rotating about a central axis; a speed reduction mechanism connected to a portion on one side in an axial direction of the motor shaft; a case accommodating the motor and the speed reduction mechanism; an output part to which rotation of the motor shaft is transmitted via the speed reduction mechanism; a rotation detector having a rotation sensor detecting rotation of the output part; and a wiring member electrically connected with the rotation sensor. The case has a first concave part located on an outer surface of the case. One end part of the wiring member penetrates the case from inside the case and protrudes inside the first concave part. The rotation sensor is located inside the first concave part and connected with one end part of the wiring member.Type: ApplicationFiled: June 14, 2019Publication date: January 2, 2020Applicant: NIDEC TOSOK CORPORATIONInventors: Hiroshi SHIRAI, Yutaka UEMATSU, Kazuhiro SAITO, Shuichi KINJO, Toshihiko AKIBA, Koichi ISHIGE
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Publication number: 20190348332Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: July 23, 2019Publication date: November 14, 2019Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20190057913Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 10163791Abstract: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.Type: GrantFiled: September 30, 2017Date of Patent: December 25, 2018Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Shuuichi Kariyazaki
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Patent number: 10134648Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: January 22, 2018Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 10128129Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.Type: GrantFiled: June 13, 2017Date of Patent: November 13, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshihiko Akiba, Hiromi Shigihara, Kei Yajima
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Publication number: 20180294239Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.Type: ApplicationFiled: February 5, 2018Publication date: October 11, 2018Inventors: Kenji SAKATA, Toshihiko AKIBA, Takuo FUNAYA, Hideaki TSUCHIYA, Yuichi YOSHIDA
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Publication number: 20180158771Abstract: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.Type: ApplicationFiled: September 30, 2017Publication date: June 7, 2018Inventors: Toshihiko AKIBA, Shuuichi KARIYAZAKI
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Publication number: 20180145001Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: January 22, 2018Publication date: May 24, 2018Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 9911673Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: April 22, 2017Date of Patent: March 6, 2018Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20170278722Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.Type: ApplicationFiled: June 13, 2017Publication date: September 28, 2017Inventors: Toshihiko AKIBA, Hiromi SHIGIHARA, Kei YAJIMA