Abstract: This work machine includes: an actuator that extends and retracts a telescopic boom; an electric drive source that is provided in the actuator and drives using power supplied from a power source; an operating unit that operates based on power of the electric drive source; an electric circuit capable of switching between a drive state in which a supply of power from the power source to the electric drive source is allowed to drive the electric drive source, and a braking state in which the supply of power from the power source to the electric drive source stops to generate a braking force to be applied to the electric drive source; and a control unit that controls the switching between the drive state and the braking state.

Abstract: A work machine includes: an actuator that extends and retracts a telescopic boom; an electric drive source that is provided in the actuator and drives using power supplied from a power source; an operating unit that operates based on power of the electric drive source; and a joint that has a drive-side element fixed to a first transmission shaft that rotates on the basis of the power of the electric drive source and a driven-side element fixed to a second transmission shaft connected to the operating unit, the joint being able to take a transmission state in which both the drive-side element and the driven-side element rotate and a non-transmission state in which only either the drive-side element or the driven-side element rotates.

Abstract: This work machine includes: an actuator that extends and retracts a telescopic boom; an electric drive source that is provided in the actuator and drives using power supplied from a power source; an operating unit that operates based on power of the electric drive source; an electric circuit capable of switching between a drive state in which a supply of power from the power source to the electric drive source is allowed to drive the electric drive source, and a braking state in which the supply of power from the power source to the electric drive source stops to generate a braking force to be applied to the electric drive source; and a control unit that controls the switching between the drive state and the braking state.

Abstract: A work machine includes: an actuator that extends and retracts a telescopic boom; an electric drive source that is provided in the actuator and drives using power supplied from a power source; an operating unit that operates based on power of the electric drive source; and a joint that has a drive-side element fixed to a first transmission shaft that rotates on the basis of the power of the electric drive source and a driven-side element fixed to a second transmission shaft connected to the operating unit, the joint being able to take a transmission state in which both the drive-side element and the driven-side element rotate and a non-transmission state in which only either the drive-side element or the driven-side element rotates.

Abstract: A terminal apparatus of a communication system is provided with an MAC section (bidirectional communication apparatus), a PHY section, a tuner, and a back-end section. The MAC section comprises a downstream data processing block having a function of substituting for a portion of the process of the CPU, a upstream data processing block having a function of substituting for a portion of the process of the CPU, a bus data arbitration processing block, a CPU bus, the CPU, and a storage apparatus. The downstream data processing block and the upstream data processing block perform direct data transmission/reception while bypassing the CPU bus.

Abstract: An interface block (11) converts the format of input downstream data (STRM). A CPU (12) receives the format-converted data (DIF) and realizes the MAC function. A TEK process block (13) receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Abstract: The encryption/decryption device includes: a data structure analysis block for receiving encrypted data or data to be encrypted and outputting control data and also the encrypted data or the data to be encrypted as processing block input data; a data control block for determining a mode selection signal according to the control data; and a shared processing block for performing encryption or decryption for the processing block input data and outputting the result. The shared processing block is configured to have the ability to perform encryption and decryption in either of the CBC mode and the CFB mode by performing ECB processing using input key data, and performs encryption or decryption in the mode indicated by the mode selection signal.

Abstract: An interface block (11) converts the format of input downstream data (STRM). A CPU (12) receives the format-converted data (DIF) and realizes the MAC function. A TEK process block (13) receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Abstract: A decoding device compares the number of errors estimated from input data syndromes by an error number estimation section with the number of errors computed by an error number computation section during decoding process, performs error correction by an error correction section based on this comparison result and the input data syndromes, performs a syndrome computation for error corrected data by a syndrome computation section again to obtain corrected data syndromes, and outputs input data as second corrected data when erroneous correction is performed or the estimated number of errors differs from the computed number of errors.

Abstract: In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.

Abstract: A terminal apparatus of a communication system is provided with an MAC section (bidirectional communication apparatus), a PHY section, a tuner, and a back-end section. The MAC section comprises a downstream data processing block having a function of substituting for a portion of the process of the CPU, a upstream data processing block having a function of substituting for a portion of the process of the CPU, a bus data arbitration processing block, a CPU bus, the CPU, and a storage apparatus. The downstream data processing block and the upstream data processing block perform direct data transmission/reception while bypassing the CPU bus.

Abstract: Improper correction is avoided in decoding of an extended Reed-Solomon code. The decoding device includes: a syndrome computation section for computing input data syndromes from input data and corrected data syndromes from first corrected data obtained from the input data; an evaluator/locator polynomial deriving section for outputting coefficients at each order of an error evaluator polynomial and an error locator polynomial obtained based on the input data syndromes, as well as error magnitudes; a Chien search section for outputting roots of the error locator polynomial; and an error correction section for outputting data obtained by performing error correction for the input data when the input data has an error while otherwise outputting the input data, as the first corrected data, and also outputting the input data obtained by restoration when the first corrected data has an error while otherwise outputting the first corrected data, as second corrected data.

Abstract: The encryption/decryption device includes: a data structure analysis block for receiving encrypted data or data to be encrypted and outputting control data and also the encrypted data or the data to be encrypted as processing block input data; a data control block for determining a mode selection signal according to the control data; and a shared processing block for performing encryption or decryption for the processing block input data and outputting the result. The shared processing block is configured to have the ability to perform encryption and decryption in either of the CBC mode and the CFB mode by performing ECB processing using input key data, and performs encryption or decryption in the mode indicated by the mode selection signal.

Abstract: A decoding device compares the number of errors estimated from input data syndromes by an error number estimation section with the number of errors computed by an error number computation section during decoding process, performs error correction by an error correction section based on this comparison result and the input data syndromes, performs a syndrome computation for error corrected data by a syndrome computation section again to obtain corrected data syndromes, and outputs input data as second corrected data when erroneous correction is performed or the estimated number of errors differs from the computed number of errors.

Abstract: Improper correction is avoided in decoding of an extended Reed-Solomon code. The decoding device includes: a syndrome computation section for computing input data syndromes from input data and corrected data syndromes from first corrected data obtained from the input data; an evaluator/locator polynomial deriving section for outputting coefficients at each order of an error evaluator polynomial and an error locator polynomial obtained based on the input data syndromes, as well as error magnitudes; a Chien search section for outputting roots of the error locator polynomial; and an error correction section for outputting data obtained by performing error correction for the input data when the input data has an error while otherwise outputting the input data, as the first corrected data, and also outputting the input data obtained by restoration when the first corrected data has an error while otherwise outputting the first corrected data, as second corrected data.

Abstract: The present invention provides a Reed-Solomon decoding apparatus comprising a device for monitoring occurrence of an error beyond an error correction capability and a degree of error correction. The Reed-Solomon decoding apparatus of the present invention comprises a Reed-Solomon decoder and a correction state monitor. The correction state monitor detects a process error in a Eucledean algorithm computer and a chain retrieval unit in the Reed-Solomon decoder, and generates a signal indicating the degree of error in input data.

Abstract: There are provided a Reed Solomon coding apparatus and a Reed Solomon coding method which are capable of performing a Reed Solomon coding process in a way adapted to case where a primitive polynomial, a generator polynomial, and a number of errors to be corrected are changed. The apparatus comprises a generator polynomial coefficient generation block 1 which receives a primitive polynomial set value 4 and a generator initial value 3 as inputs, expands the generator polynomial to generate coefficient data 8 using these values, and a data coding block 2 which receives the primitive polynomial set value 4 and divides an information polynomial by the generator polynomial using the value 4, thereby coding data.

Abstract: A waveform equalization coefficient generator for generating equalization coefficients for taps of digital filters for equalizing signal waveforms is disclosed which is smaller in circuit size and consumes less electric power in comparison with conventional waveform equalization coefficient generators. In a data selection means in a complex arithmetic unit, a first data selection unit selects between real part data and imaginary part data of an equalization coefficient, a second data selection unit selects between real part data and imaginary part data of a received signal, and a third data selection unit selects between EI (error data in the I-axis direction) and EQ (error data in the Q-axis direction). A sum-of-products means is provided which has one multiplier and one adder.

Abstract: In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.

Abstract: Integrating AFC/APC function with waveform equalization function for and reducing the circuit size of a signal wave-form equalizer apparatus. A waveform equalization section is divided into an FFE block as an anterior stage and a DFE block as a posterior stage. An AFC/APC block is provided therebetween. In the AFC/APC block, an AFC/APC coefficient update section updates a coefficient used for removing frequency and phase errors in accordance with an LMS algorithm, and a tap multiplies a modulated signal by the updated coefficient. Error data produced by an error estimation block is used by not only FFE and DFE coefficient update sections but also the AFC/APC coefficient update section for updating the coefficients. That is to say, the waveform equalization section and the AFC/APC block use the error estimation block in common, thereby reducing the circuit size considerably.