Abstract: The Reed-Solomon error-correcting circuit in accordance with a first invention is constructed so as to perform parallel operation by two-step pipelined processing in a syndrome generating circuit and an error-correcting circuit. The error-correcting circuit operates in synchronization with a clock with a period of 1/N the period of the received symbol clock, where N≧1, and N is an integer. Further, an error-locator-polynomial/error-evaluator-polynomial calculating circuit in the error-correcting circuit has a memory in which the syndrome is input and a Galois-field operations circuit that is connected to the memory. By these means, the Reed-Solomon error-correcting circuit in the present invention performs high-speed processing with small-scale hardware. Further, in an Euclid's algorithm that obtains an error-locator-polynomial, by performing Galois-field operations, from the syndrome equation S(z)=sk−1zk−1+sk−2zk−2+ . . .

Abstract: A syndrome calculation unit 101 forming a first pipeline stage, a Euclidean algorithm arithmetic operation/error value calculation unit 102 and a Chien search unit 103 together forming a second pipeline stage, and an error correction unit 105 forming a third pipeline stage are provided. The unit 102 implements, by iterative use of a single inverse element calculator, a single Galois multiplier, and a single Galois adder, the Euclidean algorithm arithmetic operation of finding an error locator polynomial .sigma.(z) and an error evaluator polynomial .omega.(z) from a syndrome polynomial S(z) and the calculation of finding an error value e.sub.u by dividing an error evaluation value .omega.(.alpha..sup.-ju) by an error locator polynomial differential value .sigma.'(.alpha..sup.-ju).

Abstract: A waveform equalization coefficient generator for generating equalization coefficients for taps of digital filters for equalizing signal waveforms is disclosed which is smaller in circuit size and consumes less electric power in comparison with conventional waveform equalization coefficient generators. In a data selection means in a complex arithmetic unit, a first data selection unit selects between real part data and imaginary part data of an equalization coefficient, a second data selection unit selects between real part data and imaginary part data of a received signal, and a third data selection unit selects between EI (error data in the I-axis direction) and EQ (error data in the Q-axis direction). A sum-of-products means is provided which has one multiplier and one adder.

Abstract: There is provided an EFM encoder comprising a DSV calculator which is smaller in circuit scale than a conventional DSV calculator. The above DSV calculator has a merging-bit DSV calculator, a frame-signal DSV/polarity evaluator, adding means, and an overflow/underflow processor. The merging-bit DSV calculator calculates merging-bit DSV data based on merging bits and on a cumulative polarity signal. The frame-signal DSV/polarity evaluator outputs frame-signal DSV data in consideration of the polarity in the final bit of the merging bits. The adding means adds up the cumulative DSV data, the merging-bit DSV data, and the frame-signal DSV data so as to calculate DSV. The overflow/underflow processor performs, when overflow or underflow has occurred in the result of calculation from the adding means, exception handling with respect to the calculation result and outputs the calculation result that has undergone the exception handling as new cumulative DSV data.