Abstract: A wafer cassette comprises a case body and an adapter that supports substrates. There are adapters of various types corresponding to the size of the substrates to be supported. The case body and the adapter of any type are united in a manner such that fitting portions of the case body are fitted individually in fitting holes of the adapter.

Abstract: There is a jump in the number of devices formed on a single wafer, and it takes a lot of time to inspect a single wafer. In addition, if wafers are inspected every lot, detected wafers remain in staying in a prober until the inspection of all of the wafers is completed. Therefore, the time required to transfer the wafers of each lot to the subsequent step is delayed. As a result, it is difficult to shorten TAT (Turn-Around-Time), and it is difficult to flexibly operate the prober.

Abstract: A conveyance system E for wafers W includes a host computer 1 for carrying out the management of the production of semiconductor devices, a plurality of probers 2 for inspecting the electric characteristics of the wafers W under the administration of the host computer 1, an AGV 3 for automatically transporting the wafers W in block of a carrier in order to deliver the wafers W one by one to these probers 2 according to respective demands and an AGV controller 4 for controlling the operation of the AGV 3 under the administration of the host computer 1.

Abstract: A wafer cassette comprises a case body and an adapter that supports substrates. There are adapters of various types corresponding to the size of the substrates to be supported. The case body and the adapter of any type are united in a manner such that fitting portions of the case body are fitted individually in fitting holes of the adapter.

Abstract: A wafer prober system includes a host computer, and a prober device. The prober device includes a plurality of prober circuits, and a plurality of touch screens, each connected to the prober circuit for simultaneously displaying image data and display data from said prober circuit, each of the prober circuit including an image processing section for sequentially photographing wafers checked by probes and outputting image data, a display control section for outputting display data according to the checking, and a prober control section for controlling the outputs of the image processing section and display control section. The control section outputs the image data and display data from the prober circuit, so that the image data and display data are displayed on the touch screen at the same time. Image data and display data are selectively provided by one of prober circuits, from image data and display data displayed on each of touch screens, and are simultaneously displayed on the host computer.

Abstract: A cassette convey means can carry a plurality of cassettes, and can selectively convey and mount a cassette to a cassette driving section, or can externally feed the mounted cassette. A cassette selection/setting means outputs designation data for selecting and designating one of the cassettes. An operation mode input means outputs an operation signal including cassette subsidiary information such as a timer setting instruction or remaining amount display data for the cassette designated by the cassette selection setting means, or a tape driving instruction. A cassette information storage means stores information of each of the plurality of cassettes. A system controller checks conditions of pieces of input information from the above-mentioned means, selects an optimal cassette according to a purpose, and controls the cassette convey means to mount the selected cassette on the tape driving section.

Abstract: A probe device having a loader unit and two measuring units is disclosed. Each of the loader and measuring units is an independent unit supported by an independent casing. Each of the loader and measuring units has its exclusive slave CPU and integrated circuit members are under the control of this slave CPU to manage operations of members at the unit. The slave CPUs are connected to a master CPU, which controls the slave CPUs and which is also an independent unit, and they are connected to one another only through the master CPU. Program language is common to the master and slave CPUs and the units can be electrically connected to form an integral control system in which signals are exchanged among the units.