Patents by Inventor Toshihiko Kasai

Toshihiko Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6940338
    Abstract: A bias circuit generates a first voltage at a first node. A second current source generates, according to the first voltage, a power supply current to be supplied to an internal circuit including transistors. A correcting transistor in a correcting circuit supplies the first node with a correcting current generated according to a constant voltage. Because of this, the first voltage is adjusted according to the correcting current. Therefore, the operating speed of the internal circuit is prevented from changing, being dependent on the variation of the threshold voltage and temperature variation of a transistor. As a result, the yield can be improved, independently of the variation of the threshold voltage among semiconductor integrated circuit chips, which occurs in a fabrication process. Further, temperature dependency of the operating speed of the internal circuit can be reduced, which can improve the yield of the semiconductor integrated circuit.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: September 6, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Kizaki, Osamu Kudo, Shinya Udo, Toshihiko Kasai
  • Publication number: 20050077957
    Abstract: An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.
    Type: Application
    Filed: March 29, 2004
    Publication date: April 14, 2005
    Inventors: Toshihiko Kasai, Shinya Udo, Masatoshi Kokubun, Yoshihiro Kizaki
  • Publication number: 20040157696
    Abstract: A differential capable of satisfying a demand for an improvement in performance and a reduction in cost in which the pinion shaft 19 is movably disposed in the differential case 2, and sliding bearings 16, 41, 42 are disposed between mutually opposite surfaces of the pair of side gears 13 and the differential case 2 and between mutually opposite surfaces of the pinions 12 and the differential case 2, respectively.
    Type: Application
    Filed: December 19, 2003
    Publication date: August 12, 2004
    Applicant: Yanagawa Seiki Co., Ltd.
    Inventors: Masahiro Saito, Kunihiro Osawa, Toshihiko Kasai
  • Publication number: 20040108889
    Abstract: A bias circuit generates a first voltage at a first node. A second current source generates, according to the first voltage, a power supply current to be supplied to an internal circuit including transistors. A correcting transistor in a correcting circuit supplies the first node with a correcting current generated according to a constant voltage. Because of this, the first voltage is adjusted according to the correcting current. Therefore, the operating speed of the internal circuit is prevented from changing, being dependent on the variation of the threshold voltage and temperature variation of a transistor. As a result, the yield can be improved, independently of the variation of the threshold voltage among semiconductor integrated circuit chips, which occurs in a fabrication process. Further, temperature dependency of the operating speed of the internal circuit can be reduced, which can improve the yield of the semiconductor integrated circuit.
    Type: Application
    Filed: November 12, 2003
    Publication date: June 10, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yoshihiro Kizaki, Osamu Kudo, Shinya Udo, Toshihiko Kasai