Patents by Inventor Toshihiko Takakura

Toshihiko Takakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4907063
    Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.
    Type: Grant
    Filed: May 20, 1987
    Date of Patent: March 6, 1990
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Daisuke Okada, Akihisa Uchida, Toshihiko Takakura, Shinji Nakashima, Nobuhiko Ohno, Katsumi Ogiue
  • Patent number: 4853343
    Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.
    Type: Grant
    Filed: March 18, 1988
    Date of Patent: August 1, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Daisuke Okada, Toshihiko Takakura, Katsumi Ogiue, Yoichi Tamaki, Masao Kawamura
  • Patent number: 4819054
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 4746963
    Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: May 24, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Daisuke Okada, Toshihiko Takakura, Katsumi Ogiue, Yoichi Tamaki, Masao Kawamura
  • Patent number: 4729965
    Abstract: This invention relates to a method of producing a semiconductor device which is suitable for forming a bipolar transistor having less fluctuation of characteristics at a high production yield.In accordance with the present invention, a graft base (or an extrinsic base) 20 is formed by doping an impurity from a polycrystalline silicon film 13, while an emitter is formed by lithographic technique.Since the emitter is formed by lithographic technique, the position at which the emitter is to be formed unavoidably changes at the time of mask alignment, but its influence upon transistor characteristics is negligible. Therefore, bipolar transistors having far more uniform characteristics can be formed far more easily than with the method which forms the emitter by self-alignment.
    Type: Grant
    Filed: April 9, 1986
    Date of Patent: March 8, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Kazuhiko Sagara, Norio Hasegawa, Shinji Okazaki, Toshihiko Takakura, Hirotaka Nishizawa
  • Patent number: 4700464
    Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: October 20, 1987
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Daisuke Okada, Akihisa Uchida, Toshihiko Takakura, Shinji Nakashima, Nobuhiko Ohno, Katsumi Ogiue