Patents by Inventor Toshihiro Miura

Toshihiro Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136491
    Abstract: A light emitting device includes a substrate and a light emitting body. The light emitting body includes a plurality of light emitting elements and an insulating body in which the plurality of light emitting elements is embedded except for a light emitting surface of the plurality of light emitting elements. The plurality of light emitting elements is formed from a singulated compound semiconductor layer and is arranged in a row direction and a column direction. The substrate includes a drive circuit, a first terminal, and a second terminal and is joined to the light emitting body. The drive circuit drives the plurality of light emitting elements. The first terminal and the second terminal electrically couple the drive circuit and the plurality of light emitting elements to each other.
    Type: Application
    Filed: February 21, 2022
    Publication date: April 25, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Toshihiro MIURA, Toshiaki HASEGAWA, Toru SASAKI, Hiroyuki KASHIHARA
  • Patent number: 11945509
    Abstract: A vehicle body rear part structure includes a rear frame and a beam member. The rear frame has: a first inner bead, a first outer bead, a second inner bead, and a second outer bead. The first inner bead and the first outer bead are formed on an inner wall and an outer wall, respectively, in a region close to the beam member. The second inner bead and the second outer bead are formed on the inner wall and the outer wall, respectively, in a region that is separated to a vehicle body frontward direction from the first beads. The first outer bead is formed to have a higher fragility than the first inner bead.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 2, 2024
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Shungo Chino, Yuya Akaba, Toshihiro Yamaguchi, Kyosuke Yamakita, Yusuke Miura, Dai Kamata, Chihiro Sakagami, Kosuke Fushimi, Shohei Ohtsuka, Hitomi Yamada
  • Publication number: 20230215904
    Abstract: A light-emitting device includes: a light-emitting element provided separately for each of pixels; a pixel electrode provided on a side of a first surface of the light-emitting element, the pixel electrode being provided for each of the pixels; a common electrode provided on a side of a second surface of the light-emitting element, the second surface being opposite to the first surface, the common electrode being provided separately for each of the pixels that are adjacent to each other; and an electrode coupler that electrically couples a plurality of the common electrodes provided for the respective pixels to each other in a plane region that is different from a plane region in which the light-emitting element is provided.
    Type: Application
    Filed: May 7, 2021
    Publication date: July 6, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroyuki KASHIHARA, Toshihiro MIURA, Toshiaki HASEGAWA
  • Publication number: 20210187898
    Abstract: Disclosed herein is a laminated structure including a first layer covering a substrate and a raised portion existing on the substrate, and a second layer covering the first layer, in which a first seam is formed inside the first layer, starting from a part at which the raised portion rises from the substrate or a vicinity of the rising part as a start point, a second seam is formed inside the second layer, starting from a part at which the first layer positioned above the substrate rises or a part of the second layer corresponding to a vicinity of the rising part as a start point, and the first seam and the second seam are discontinuous.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Applicant: SONY CORPORATION
    Inventor: Toshihiro MIURA
  • Patent number: 10889082
    Abstract: Disclosed herein is a laminated structure including a first layer covering a substrate and a raised portion existing on the substrate, and a second layer covering the first layer, in which a first seam is formed inside the first layer, starting from a part at which the raised portion rises from the substrate or a vicinity of the rising part as a start point, a second seam is formed inside the second layer, starting from a part at which the first layer positioned above the substrate rises or a part of the second layer corresponding to a vicinity of the rising part as a start point, and the first seam and the second seam are discontinuous.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: January 12, 2021
    Assignee: Sony Corporation
    Inventor: Toshihiro Miura
  • Publication number: 20200251516
    Abstract: The present disclosure relates to a semiconductor device, a solid-state image sensor, a manufacturing method, and an electronic device that can promote stabilization of device characteristics. The solid-state image sensor is provided with a pixel region that is a region where a pixel is formed on a semiconductor substrate, and a peripheral region that is a region where a pixel is not formed on the semiconductor substrate. Then, a stopper layer is formed in the semiconductor substrate at a predetermined depth in the peripheral region with a material different from that of the semiconductor substrate, and a dug portion is formed by digging the pixel region and the peripheral region of the semiconductor substrate to a depth corresponding to the stopper layer. At this time, the end point of the processing time for digging the dug portion is determined by utilizing the detection of a compound containing the material of the stopper layer. The present technology can be applied to a CMOS image sensor, for example.
    Type: Application
    Filed: October 12, 2018
    Publication date: August 6, 2020
    Inventor: TOSHIHIRO MIURA
  • Publication number: 20190118503
    Abstract: Disclosed herein is a laminated structure including a first layer covering a substrate and a raised portion existing on the substrate, and a second layer covering the first layer, in which a first seam is formed inside the first layer, starting from a part at which the raised portion rises from the substrate or a vicinity of the rising part as a start point, a second seam is formed inside the second layer, starting from a part at which the first layer positioned above the substrate rises or a part of the second layer corresponding to a vicinity of the rising part as a start point, and the first seam and the second seam are discontinuous.
    Type: Application
    Filed: March 24, 2017
    Publication date: April 25, 2019
    Applicant: SONY CORPORATION
    Inventor: Toshihiro MIURA
  • Patent number: 10217666
    Abstract: A stacked structure, includes: a wiring; an insulating layer; a substrate; and a protective layer, wherein the wiring, the insulating layer, and the substrate are stacked from a bottom side, and an end portion of the wiring is projected from a side face of the stacked structure, and the protective layer is provided between the insulating layer and at least a part of the wiring and is configured of a material different from a material configuring the insulating layer.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 26, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Toshihiro Miura, Tomohide Naka, Toshiaki Hasegawa
  • Patent number: 9786708
    Abstract: A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 10, 2017
    Assignee: Sony Corporation
    Inventors: Tetsuji Yamaguchi, Kazunori Nagahata, Toshihiro Miura, Kaori Takimoto
  • Publication number: 20160064440
    Abstract: A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: Tetsuji Yamaguchi, Kazunori Nagahata, Toshihiro Miura, Kaori Takimoto
  • Patent number: 9219100
    Abstract: A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: December 22, 2015
    Assignee: Sony Corporation
    Inventors: Tetsuji Yamaguchi, Kazunori Nagahata, Toshihiro Miura, Kaori Takimoto
  • Publication number: 20140291857
    Abstract: A stacked structure, includes: a wiring; an insulating layer; a substrate; and a protective layer, wherein the wiring, the insulating layer, and the substrate are stacked from a bottom side, and an end portion of the wiring is projected from a side face of the stacked structure, and the protective layer is provided between the insulating layer and at least a part of the wiring and is configured of a material different from a material configuring the insulating layer.
    Type: Application
    Filed: March 20, 2014
    Publication date: October 2, 2014
    Applicant: Sony Corporation
    Inventors: Toshihiro Miura, Tomohide Naka, Toshiaki Hasegawa
  • Publication number: 20140209876
    Abstract: A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 31, 2014
    Applicant: Sony Corporation
    Inventors: Tetsuji Yamaguchi, Kazunori Nagahata, Toshihiro Miura, Kaori Takimoto
  • Patent number: 7650133
    Abstract: Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: January 19, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Toshihiro Miura, Hitoshi Akamine, Yasushi Shigeno, Akishige Nakajima, Masahiro Tsuchiya
  • Publication number: 20070093552
    Abstract: The invention provides an early insulin secretion stimulator consisting of corosolic acid, etc. The early insulin secretion stimulator of the invention is capable of rapidly inducing secretion of insulin immediately after meals without inducing secretion of excess insulin in the absence of blood glucose increase.
    Type: Application
    Filed: September 22, 2004
    Publication date: April 26, 2007
    Inventors: Futoshi Matsuyama, Yutaka Seino, Mitsuo Fukushima, Toshihiro Miura, Takeshi Fujita, Tetsuo Kaneko
  • Patent number: 7192532
    Abstract: A tungsten silicide layer (104) is etched by plasma etching using Cl2+O2 gas as etching gas. When etching of the tungsten silicide layer (104) is ended substantially, etching gas is switched to Cl2+O2+NF3 and over etching is performed by plasma etching. Etching process is ended under a state where a polysilicon layer (103) formed beneath the tungsten silicide layer (104) is slightly etched uniformly. Residual quantity of the polysilicon layer (103) can be made uniform as compared with prior art and a high quality semiconductor device can be fabricated stably.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: March 20, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Koh, Toshihiro Miura, Takayuki Fukasawa, Akitaka Shimizu, Masato Kushibiki, Asao Yamashita, Fumihiko Higuchi
  • Publication number: 20070049237
    Abstract: Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 1, 2007
    Inventors: Toshihiro Miura, Hitoshi Akamine, Yasushi Shigeno, Akishige Nakajima, Masahiro Tsuchiya
  • Publication number: 20060261460
    Abstract: An electrode on a main surface of a module board, to which an emitter electrode of a semiconductor chip formed with a switching element of a power supply control circuit that supplies a power supply voltage to amplifier circuit parts of a power module of a digital cellular phone is electrically connected to a wiring in an internal layer of the module board through a plurality of viaholes. Further, the wiring CL1 is electrically connected to an electrode for the supply of the power supply voltage, which is provided on a back surface of the module board. Accordingly, an output characteristic of the semiconductor device is improved.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Inventors: Yusuke Sato, Kenji Koyama, Toshihiro Miura, Toshihiko Kyogoku
  • Publication number: 20060235078
    Abstract: The present invention provides early insulin secretion stimulators consisting of triterpenes represented by the following general formula (1) and/or triterpenes represented by the following general formula (2). [where R1 represents COOH, etc., R11 and R12 represent CH2OH, etc., X1 represents hydrogen or OH and X11, X12, X21 and X22 represent OH, etc.
    Type: Application
    Filed: June 20, 2006
    Publication date: October 19, 2006
    Inventors: Futoshi Matsuyama, Yutaka Seino, Mitsuo Fukushima, Toshihiro Miura, Takeshi Fujita, Tetsuo Kaneko
  • Publication number: 20060193895
    Abstract: An additive for food and beverage, comprising a compound represented by the general formula (1) or a salt thereof: wherein R1 to R4 are each a glycoside group, a hydroxyl group, or a hydrogen atom, R5 is a carboxyl group and R6 to R8 are each a methyl group or a hydrogen atom.
    Type: Application
    Filed: February 25, 2005
    Publication date: August 31, 2006
    Inventor: Toshihiro Miura