Abstract: A knowledge inferential processing apparatus comprises an external interface section for inputting and outputting information between the knowledge inferential processing apparatus and the exterior thereof; a rule base memory for representing knowledge as a combination of a plurality of rules constructing a premise conditional section and a conclusive section as a pair, and storing the represented knowledge; a rule pointer table for storing a rule pointer group indicative of a sequence for applying the rules within the rule base memory; an inferential processing section for interpreting and executing the rules and judging whether or not the matching is formed with respect to the respective rules; a memory section for storing fact data sent to the inferential processing section and conclusive data generated during the inferential processing; an inferential hysteresis recording section for recording a rule pointer of the matched rule in the matched sequence with respect to the inferential processing results exe

Abstract: A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.