Patents by Inventor Toshiji Hamatani

Toshiji Hamatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090253251
    Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.
    Type: Application
    Filed: November 12, 2008
    Publication date: October 8, 2009
    Applicants: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., SHARP KABUSHIKI KAISHA
    Inventors: Misako NAKAZAWA, Toshiji HAMATANI, Naoki MAKITA
  • Patent number: 7569408
    Abstract: An insulated gate field effect semiconductor device comprising a substrate having provided thereon a thin-film structured insulated gate field effect semiconductor device, said device being characterized by that it comprises a metal gate electrode and at least the side thereof is coated with an oxide of the metal. The insulated gate field effect semiconductor device according to the present invention is also characterized by that the contact holes for the extracting contacts of the source and drain regions are provided at about the same position of the end face of the anodically oxidized film established at the side of the gate. Furthermore, the present invention provides a method for forming insulated gate field effect semiconductor devices using less masks.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: August 4, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akira Mase, Toshiji Hamatani
  • Publication number: 20090186469
    Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.
    Type: Application
    Filed: April 1, 2009
    Publication date: July 23, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
  • Patent number: 7521699
    Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: April 21, 2009
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
  • Publication number: 20090008643
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Application
    Filed: July 30, 2008
    Publication date: January 8, 2009
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Publication number: 20080308830
    Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.
    Type: Application
    Filed: July 25, 2008
    Publication date: December 18, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 7456056
    Abstract: A novel and very useful method for forming a crystal silicon film by introducing a metal element which promotes crystallization of silicon to an amorphous silicon film and for eliminating or reducing the metal element existing within the crystal silicon film thus obtained is provided. The method for fabricating a semiconductor device comprises steps of intentionally introducing the metal element which promotes crystallization of silicon to the amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain the crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere; eliminating a thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the region from which the thermal oxide film has been eliminated by implementing another thermal oxidation.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: November 25, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 7456430
    Abstract: The invention primarily provides gate electrodes and gate wirings permitting large-sized screens for active matrix-type display devices, wherein, in order to achieve this object, the construction of the invention is a semiconductor device having, on the same substrate, a pixel TFT provided in a display region and a driver circuit TFT provided around the display region, wherein the gate electrodes of the pixel TFT and the driver circuit TFT are formed from a first conductive layer, the gate electrodes are in electrical contact through connectors with gate wirings formed from a second conductive layer, and the connectors are provided outside the channel-forming regions of the pixel TFT and the driver circuit TFT.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: November 25, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Toru Takayama, Toshiji Hamatani
  • Patent number: 7452791
    Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: November 18, 2008
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
  • Patent number: 7427780
    Abstract: There is disclosed a method of fabricating a thin-film transistor having excellent characteristics. Nickel element is held in contact with selected regions of an amorphous silicon film. Then, thermal processing is performed to crystallize the amorphous film. Subsequently, thermal processing is carried out in an oxidizing ambient containing a halogen element to form a thermal oxide film. At this time, the crystallinity is improved. Also, gettering of the nickel element proceeds. This crystalline silicon film consists of crystals grown radially from a number of points. Consequently, the thin-film transistor having excellent characteristics can be obtained.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: September 23, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 7420210
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: September 2, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Patent number: 7417253
    Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: August 26, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 7391054
    Abstract: The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 24, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Publication number: 20080070389
    Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.
    Type: Application
    Filed: November 28, 2007
    Publication date: March 20, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
  • Patent number: 7315035
    Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: January 1, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
  • Publication number: 20070138954
    Abstract: (OBJECT) The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. (MEANS FOR SOLVING THE PROBLEM) In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member.
    Type: Application
    Filed: February 5, 2007
    Publication date: June 21, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno, Masakazu Murakami, Toshiji Hamatani, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 7180093
    Abstract: The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: February 20, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno, Masakazu Murakami, Toshiji Hamatani, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 7173282
    Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, the crystallinity is improved and the gettering of nickel elements proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: February 6, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
  • Publication number: 20070001236
    Abstract: The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.
    Type: Application
    Filed: September 6, 2006
    Publication date: January 4, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 7141462
    Abstract: There are provided a substrate of a semiconductor device and a fabrication method thereof which suppress impurity from turning around from a glass or quartz substrate in fabrication steps of a TFT. An insulating film is deposited so as to surround the glass substrate by means of reduced pressure thermal CVD. It suppresses the impurity from infiltrating from the glass substrate to an active region of the TFT in the later process.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: November 28, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Shunpei Yamazaki, Hisashi Ohtani, Satoshi Teramoto, Toshiji Hamatani