Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit stores management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of the management information in a latest state and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.

Abstract: According to the embodiments, a first management table, which is included in a nonvolatile second semiconductor memory and manages data included in a second storage area by a first management unit, is stored in the second semiconductor memory and a second management table for managing data in the second storage area by a second management unit larger than the first management unit is stored in a first semiconductor memory capable of random access.

Abstract: According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.

Abstract: According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.

Abstract: According to one embodiment, a controller reads out the non-volatile address management information required to execute one of the read commands into an address information cache and retrieves data from the nonvolatile memory according to the volatile address management information stored in the address information cache. In addition, the controller among the read commands stored in the command queue, preferentially executes the read command whose logical addresses are all found in the volatile address management information.

Abstract: According to an embodiment, a semiconductor storage device includes an error correction processing unit that executes encoding process related data to be dispersedly written over a plurality of memory areas and decoding process related data dispersedly written over the plurality of memory areas. A transfer management unit determines whether or not data related to the data transfer request is a target of the error correction process and causes the error correction processing unit to execute the error correction process only with respect to the data determined as the target of the error correction process.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory, a temporary storage buffer that temporarily stores writing data to be written to the nonvolatile semiconductor memory, and a coding processing unit that divides coding target data of an error correction code into two or more divided data and writes an error correction code obtained by performing an error correction coding process based on the divided data stored in the temporary storage buffer to the temporary storage buffer as an intermediate code.

Abstract: A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.

Abstract: An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information and the defective information. The second storage has storage regions in a number larger than the first number. The input unit inputs data to the second storage by the first number at a time. The shift number determining unit determines a shift number. The output unit outputs the data stored in the storage regions which is after a head storage region by the shift number, as the data is to be supplied to the data line having no defect sector based upon the defective information, and outputs information that differs from the data to the defective data line.

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract: A forward lookup address translation table and a reverse lookup address translation table stored in a nonvolatile second storing unit are transferred as a master table to a volatile first storing unit at a time of start-up. When an event occurs so that the master table needs to be updated, difference information before and after update of any one of the forward lookup address translation table and the reverse lookup address translation table is recorded in the first storing unit as a log, thereby reducing an amount of the log.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A method, to be executed by an application program according to an embodiment, for controlling a memory system provided with a nonvolatile memory includes: acquiring an unused memory area from an operating system installed in an information processing apparatus provided with the memory system; prohibiting the acquired unused memory area from being used by any application program other than the above application program; acquiring the address of the acquired unused memory area; and notifying the address of the acquired unused memory area to the memory system. In the method according to an embodiment for controlling a memory system, prohibition state put by the prohibiting is preserved until receiving a change instruction.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks, a volatile memory storing management information including a storage position of data stored in the nonvolatile memory, a management information writing unit, and a management information storing unit. The management information writing unit is configured to update, when the storage position of data is changed in the nonvolatile memory, the management information stored in the volatile memory. The management information storing unit is configured to, before writing data to the nonvolatile memory, store a first log including an update schedule of the management information in the nonvolatile memory and, after writing data to the nonvolatile memory, store a second log including an update result of the management information in the nonvolatile memory, wherein the management information storing unit is configured to store the first log and the second log in the same-numbered page of the different two blocks.

Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Abstract: A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.