Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer 12, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

Abstract: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

Abstract: A pulse generating circuit generates a pulse with a desired pulse width even when a process parameter for manufacturing fluctuates or a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and operating to output a first voltage changing from a high level towards a low level based on a first time constant according to a one-shot pulse, a second voltage outputting section having a second delay circuit and operating to output a second voltage changing from a low level towards a high level based on a second time constant according to the one-shot pulse, and a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting the one-shot pulse to a cross time point when the first voltage coincides with the second voltage.

Abstract: A method of manufacturing a semiconductor device include a step of forming an insulating layer, which is obtained by building up a first oxide film, a nitride film and a second oxide film on a substrate in the order mentioned, and a Salicide step of forming a Salicide-structure gate electrode on the insulating film. A silicidation reaction between the substrate surface and an N+ diffusion region is prevented in the Salicide step by causing the insulating layer to remain even in a region on the substrate besides that immediately underlying the gate electrode.

Abstract: Disclosed is a device and a method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high voltage withstand type, to prevent the voltage from being decreased at the time of programming, to prevent the readout current from being decreased and to provide a constant sum resistance of the electrically conductive regions without dependency upon the memory cell locations.

Abstract: A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

Abstract: A pulse generating circuit is provided which is capable of generating a pulse with a desired pulse width even when a process parameter for manufacturing, especially a threshold voltage of a MOS (Metal Oxide Semiconductor) transistor fluctuates or even when a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and operating to output a first voltage changing from a high level towards a low level based on a first time constant according to a one-shot pulse, a second voltage outputting section having a second delay circuit and operating to output a second voltage changing from a low level towards a high level based on a second time constant according to the one-shot pulse, and a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting the one-shot pulse to a cross time point when the first voltage coincides with the second voltage.

Abstract: A method of manufacturing a semiconductor device include a step of forming an insulating layer, which is obtained by building up a first oxide film, a nitride film and a second oxide film on a substrate in the order mentioned, and a Salicide step of forming a Salicide-structure gate electrode on the insulating film. A silicidation reaction between the substrate surface and an N+ diffusion region is prevented in the Salicide step by causing the insulating layer to remain even in a region on the substrate besides that immediately underlying the gate electrode.

Abstract: According to the present invention, a voltage of 10.5 V, a voltage of 6.5 V and a voltage of 0.5 V are respectively applied to the control gate, the drain and the source of a memory cell that is a programming target. And a voltage of 0 V (a ground voltage) is applied to the control gate of a memory cell that is not a programming target and that does not belong to the row in which of the programming target memory cell is located. As a result, it is ensured that the memory cell that is not the programming target is non-conductive, and that the drain-substrate electrical field of the memory cell that is the programming target is reduced.

Abstract: Disclosed are device and method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high voltage withstand type, to prevent the voltage from being decreased at the time of programming and to prevent the readout current from being decreased and to provide a constant sum resistance of the electrically conductive regions without dependency upon the memory cell locations. In a pair of two electrically conductive regions, provided for extending parallel to and in separation from each other on a substrate surface, one longitudinal end of one of the electrically conductive regions is diagonally connected to the other longitudinal end of the other electrically conductive region by a wiring to form a set of sub bit lines. On both ends of the memory cell array, there are provided selection transistors for interconnecting the sub bit lines and main bit lines.

Abstract: A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

Abstract: A flash memory erase operation controller has a common discharge circuit which directly electrically connects at least one of a source, a drain, and a substrate making up memory cells forming a flash memory to a gate during an erase operation in the flash memory.

Abstract: To provide a semiconductor storage apparatus capable of reducing a chip area, one main bit line is provided to a plurality of sub bit lines commonly connected with drains of memory cell transistors, the plurality of the bit lines are connected to ends on one side of switches at a first stage, control terminals of which are respectively inputted with column selecting signals and ends on other side of the switches are commonly connected and connected to the main bit line via a switch at a second stage, a control terminal of which is inputted with a column selecting signal, the sub bit lines are wired to a first wiring layer, the main bit line is wired to a second wiring layer and the second wiring layer is wired with power source lines, lines of voltage control signals in erasing or writing and high voltage power supply lines in regions among the main bit lines.

Abstract: A flash memory erase operation controller has a common discharge circuit which directly electrically connects at least one of a source, a drain, and a substrate making up memory cells forming a flash memory to a gate during an erase operation in the flash memory.

Abstract: There is provided a word-line driving circuit has: two P-channel type transistors which are connected in a flip-flop configuration and one of which is connected between a first power supply and a word line; an N-channel transistor which is connected between a signal obtained by decoding a low-order address and a gate of the above-mentioned one P-channel type transistor and which has its gate connected with a signal obtained by decoding a high-order address; a first NN-channel type transistor which is connected between a word line and a second power supply and which has its gate connected with the signal obtained by decoding a low-order address; and a second NN-channel type transistor which is connected between a word line and the second power supply and which has its gate connected with the signal obtained by decoding a high-order address.

Abstract: A boosting stage of a charge pump circuit has a boosting capacitor connected to a boosted node and an n-channel enhancement type field effect transistor connected between the boosted node and other node and fabricated on a p-type well connected to the other node, and the n-channel enhancement type field effect transistor turns on for discharging current from the other node to the boosted node through the conductive channel and the p-n junction between the p-type well and the n-type source node thereof so that the potential level at the p-type well restricts the back-gate biasing effect, thereby widely swinging the potential level at the other node.

Abstract: To provide a pull-up circuit and a pull-down circuit having the same withstand voltage performance to other neighboring circuit elements without needing special layout consideration, a pull-up circuit of the invention having an nMOS pull-up transistor (N1) connected between a first node (A2) and a pull-up node (OU) comprises a pMOS transistor (P2), a drain of said pMOS transistor (P2) connected to the first node (A2), a source and a substrate of said pMOS transistor (P2) connected to a positive power supply (Vcc), and a gate of said pMOS transistor (P2) controlled with a pull-up signal; and a pull-down circuit of the invention having a pMOS transistor (P1) connected between a first node (B2) and a pull-down node (OD) comprises an nMOS transistor (N2), a drain of said nMOS transistor (N2) connected to the first node (B2), a source and a substrate of said nMOS transistor (N2) connected to a negative power supply (GND), and a gate of said nMOS transistor (N2) controlled with a pull-down signal.

Abstract: A semiconductor device comprising a substrate having thereon an active area including a plurality of MOS transistors, an inactive area, and adjacent gate wires having walls and a sidewall on the walls of the gate wires. The adjacent gate wires are arranged on the active area and on the inactive area. A first interval between the adjacent gate wires on the active area is greater than a second interval between the adjacent gate wires on the inactive area. The active area includes one of a source and drain region formed by introducing an impurity in an interval between the adjacent gate wires. This structure circumvents the problem which would otherwise occur when the active area between the adjacent gate wires is covered by the sidewalls to thereby block ion implantation. Also, the overall size of the semiconductor device can be reduced and the wiring density can be increased.

Abstract: A plurality of memory cells are arranged in lattice arrangement to form a memory cell array. Each of the memory cells is provided with a source. Data in the memory cell can be electrically written and erased. Sources of all the memory cells are connected in common. Also, a source voltage control circuit having two or more kinds of load characteristics is connected to the sources connected in common. According to a load characteristics selected from a plurality of load characteristics, source voltage of the memory cell is controlled.

Abstract: A power supply switching circuit comprises first and second PMOSFETs connected in series between a writing high voltage and an output terminal in the named order, and third and fourth PMOSFETs connected in series between a reading voltage and the output terminal in the named order. A substrate potential of the first PMOSFET is connected to the writing high voltage, and a substrate potential of the third PMOSFET is connected to the reading voltage. A substrate potential of the second and fourth PMOSFETs are connected in common to a substrate potential control circuit which is configured to selectively supply either the writing high voltage or the reading voltage to the common connected sub.about.t rate potential of the second and fourth PMOSFETs.