Abstract: An entire erasing period for a non-volatile semiconductor memory is divided into a first erasing mode and a second erasing mode. In the first erasing mode, a positive voltage is applied to sources of memory cells MC00 through MCmn with gates of the memory cells at a ground potential to carry out the erasing operation until an erasing voltage VTM2 that is higher than a final erasing voltage VTM1 is obtained. In the second erasing mode, negative and positive voltages are applied to the gates and the sources, respectively, of the memory cells to carry out the erasing operation until the final erasing voltage VTM1 is obtained.

Abstract: In non-volatile semiconductor memory erasing method and device, in an erasing operation, a negative potential is applied to the gate of each memory cell (MC00 to MCmn), a positive potential which is equal or above a supply voltage Vcc from the external is applied to the channel of each memory cell, and the source and drain of each memory cell are connected to the ground potential through a high-resistant current path by a cell voltage control circuit, thereby obtaining a stable erasing characteristic in the erasing operation.

Abstract: Step S1 is carried out to lower, at the beginning of erasing operation, a voltage across a drain of a memory cell below a positive voltage applied to a source for erasing and then step S2 is carried out to open the drain. At the beginning of the erasing operation, step S3 is carried out to apply the positive voltage to the source and then step S3-1 is carried out to apply a negative voltage to a gate. To complete the erasing operation, step S4 is carried out to force the gate to be at the ground level and then the source to be at the ground level.

Abstract: In a charge pump circuit having a plurality of transistors connected in a diode configuration, the threshold voltage of the transistors are prevented from being increased due to a back-bias effect by having the threshold biases of the transistors adjusted. The circuit, therefore, ensures a desired voltage boosting ability.

Abstract: A nonvolatile semiconductor memory includes a cell array prepared by arranging erasable and programmable memory cell transistors in rows and columns, word lines arranged in correspondence with the respective rows of the cell array and connected to the control gates of the memory cell transistors, digit lines arranged in correspondence with the respective columns of the cell array and connected to the drains of the memory cell transistors, source lines connected to the sources of the memory cell transistors, and a source power supply circuit for applying a source voltage to the source lines in an erase operation. This memory erases by the source voltage data in the memory cell transistors in the rows and columns of the cell array.

Abstract: In a sense amplifier for use in a semiconductor memory having a plurality of memory cells, comprising first and differential amplifiers receiving a potential signal read out from a selected memory cell and a reference potential, and having an output for respectively outputting first and second outputs differentially amplified in a phase opposite to each other, a CMOS inverter circuit is composed of a PMOS transistor and a NMOS transistor having their gate connected in common to receive the output of second differential amplifier. The CMOS inverter circuit has a threshold level corresponding to an intermediate level between a high logic level and a low logic level of binary information.

Abstract: A flash memory cell array MC having an array construction of a virtual grounding type wherein a column line B5 on one-end within the array MC is connected to a sense circuit AMP through a N-type MOSFET MV1. On erase verify, a column line B1 on another end is set to ground potential through an N-type MOSFETs MS1 and MS4. By selecting a row line W1, a current flowing from the column line B5 to the column B1 through memory elements M11 to M14 connected to the row line W1 is inspected by a sense circuit AMP, and the memory elements M11 to M14 are erase-verified at the same time.

Abstract: In a virtual ground type nonvolatile semiconductor device including row lines, column lines, and floating-gate type nonvolatile memory cells, each connected between two adjacent column lines and controlled by one of the row lines, during a read mode, one of the row lines is made a high level, and two adjacent column lines are subject to a data read operation. At this time, two column lines each immediately on one side of the two adjacent column lines are made a low level. During a write mode, one of the row lines is made a high level, and two adjacent column lines are made at the low level. At this time, two column lines each immediately on one side of the two adjacent column lines are subject to a write operation.

Abstract: A semiconductor device includes a P-type semiconductor substrate, an N-type well region formed on the surface of the substrate, a P-type well region formed in the N-type well region and a MOSFET as a flash memory element formed in the P-type well region. Upon erasure of the information in the flash memory, a high voltage is temporarily charged to the P-type and N-type well regions, in such a manner that a first high voltage pulse of a predetermined width is charged to the N-type well region, a second high voltage pulse having a pulse width narrower than the pulse width of the first pulse is charged to the P-type well region in a period between the initiation end and the termination end of the first pulse.

Abstract: A semiconductor memory device has a matrix of memory cells interconnected by a plurality of column and row lines to form a channel between one of the column lines and a voltage source corresponding to a specified status. A sensing circuit connects or disconnects an output node where the current is supplied from the voltage source with the input node which indicates the status of the specified memory cell. A reference voltage generation circuit generates the reference voltage. A comparison circuit generates a signal to indicate the specified status of the selected memory cell. Between the output and input nodes of the sensing circuit, a first transistor under gate control by a reverse voltage of the input node voltage is connected and between the input node of the sensing circuit and the input node of the reference voltage generation circuit, a second transistor under gate control by the reverse voltage is also provided.

Abstract: A data read-out circuit in the semiconductor memory device has a sense circuit which detects the state of a selected memory cell and outputs a sense output voltage, a reference voltage generating circuit which outputs a reference voltage, and a comparison amplifier which compares the sense output voltage with the reference voltage and outputs an output voltage. The data read-out circuit further has a reference voltage control circuit consisting of a P-channel MOSFET connected between a power supply source and an output node of the reference voltage generating circuit. A gate of the P-channel MOSFET receives the sense output voltage from the sense circuit.

Abstract: A row decoding circuit for an EEPROM is described. The row decoding circuit includes a first circuit and a second circuit. The first circuit delivers to a word line a predetermined dc voltage in response to a decode signal during both read operation and write operation and stops delivering the predetermined dc voltage when the word line is selected during erase operation. The predetermined dc voltage is the read voltage when the word line is selected during read operation, is the write voltage when the word line is selected during write operation and is a prescribed voltage level when the word line is not selected during either read operation or write operation. The second circuit delivers to the word line a negative erasure voltage in response to the decode signal when the word line is selected during erase operation and stops delivering any voltage to the word line when the word line is not selected during erase operation.

Abstract: An output buffer has a series circuit connected between a first and a second power supply terminal, which circuit is formed by a first n-channel MOSFET whose gate receives a first output data control signal and a second n-channel MOSFET whose gate receives a second output data control signal. The output buffer further has a third N-channel MOSFET connected between a bonding pad and a common junction node defined by the first and second N-channel MOSFETs. The third N-channel MOSFET has a gate connected to the first power supply terminal so that it is controlled to be always in a conductive state. The output buffer is effectively increased or enhanced in its resistance against electrostatic breakdown.

Abstract: An electrically programmable read only memory device memorizes data bits in memory cells each implemented by a pair of floating gate type field effect transistors, and first and second current mirror circuits supplies currents to a pair of digit lines coupled to the pair of floating gate type field effect transistors for producing a difference in voltage level indicative of the read-out data bit which is quickly converted into a voltage level with a third current mirror circuit, wherein the ratio of conductances of first and second current paths of the third current mirror circuit is controlled by a ratio controlling circuit depending upon an output data signal so that an output inverting circuit coupled with the third current mirror circuit never transiently shifts the voltage level of the output data signal upon changing the memory cell to be accessed.

Abstract: An output buffer circuit includes a first MOSFET provided between a power supply and an output data terminal and a second MOSFET provided between the output data terminal and the ground. The first and second MOSFETs become ON or OFF state in accordance with outputs of first and second inverter circuits which are controlled by an output potential detecting circuit which detects an output level of the output buffer circuit to avoid the decrease of the ground potential level.

Abstract: For presenting a multipurpose signal pin provided in a semiconductor memory device from undesirable internal leakage current, a signal distributing unit has an inverter circuit responsive to a first external signal of either first and second voltage level for providing the second and first voltage level to a first internal control signal line and a gating circuit operative to block the first external signal but to transfer a second external signal of an extremely high voltage level to a second internal control signal line, and the gating circuit comprises a limiter transistor operative to keep off in the presence of the second external signal but to provide the second voltage level in the presence of the first external signal and a series combination of first and second gating transistors coupled to the multipurpose signal pin and associated with a voltage control circuit for producing gate control signals fed to the first and second gating transistors as well as a back gate biasing signal fed to the second g

Abstract: A sense circuit incorporated in a semiconductor memory device has a conduction path between a specified non-volatile memory cell and a source of constant voltage level for deciding the logic level of the data bit read out form the memory cell, and the conduction path is divided into a plurality of channels formed in field effect transistors arranged in parallel and different in threshold voltage for improving an access time without sacrifice of a low sensitivity to noises, so that the conduction path is increased in current driving capability, thereby allowing a parasitic capacitance to rapidly be charged up.

Abstract: A redundant address memory circuit is used in a memory element exchange circuit associated to a memory matrix composed of FAMOS memory cells and provided with a redundant memory array composed of FAMOS memory cells. The redundant address memory circuit comprises a FAMOS memory cell for storing a defective address, and an output circuit connected to the defective address storing FAMOS memory cell for generating an output signal corresponding to the content of the defective address storing FAMOS memory cell. In addition, there is provided a circuit connected to the defective address storing FAMOS memory cell and to the output circuit for receiving the content of the defective address storing FAMOS memory cell through the output circuit so as to write the content of the defective address storing FAMOS memory cell into the defective address storing FAMOS memory cell when a new data is written to the memory matrix.

Abstract: A circuit for producing a constant voltage comprises first and second MOSFETs, and first and second bias voltage producing devices. The first and second MOSFETs to which first and second input voltages are applied, respectively, are connected in series. The first bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the first MOSFET, to be applied across drain and gate of the first MOSFET, and the second bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the second MOSFET, to be applied across drain and gate of the second MOSFET, so that a wide range of an output voltage is produced at a connecting point of the first and second MOSFETs. Even more, the output voltage is stabilized in level, even if the threshold voltages fluctuate in a semiconductor device fabricating process.

Abstract: A control circuit provided in association with a multi-purpose input node is provided with an input signal detecting circuit for relaying a middle voltage level from the multipurpose input node to the internal circuit, a charge-pump circuit activated in the presence of a high voltage level for producing an extremely high voltage level, a transferring circuit coupled between the multipurpose input node and the charge-pump circuit, and a gate transistor coupled between the multipurpose input node and the output node, and the extremely high voltage level is supplied to not only the gate transistor but also the transferring circuit, so that the high voltage level is fully transferred to the charge-pump circuit, thereby allowing the gate transistor to transfer the high voltage level to the output node without any reduction in voltage level.