Abstract: This connector can be connected to a counterpart connector having a counterpart contact, and is provided with an electric current sensor function. Specifically, the connector is provided with a contact, a protective member composed of an insulating material, a core, and an electric current detection member. The contact extends along the longitudinal direction so as to have a longitudinal part that can be connected to the counterpart contact. The protective member surrounds the contact in the plane orthogonal to the longitudinal direction. The core surrounds the protective member in the plane orthogonal to the longitudinal direction. The core has a gap. The electric current detection member is at least partially disposed within the gap.

Abstract: A geomagnetic sensor includes: a core that constitutes a closed magnetic circuit; a pair of coils that are wound around the core in positions facing each other and are connected in series to generate magnetic flux in the same circumferential direction in the core; an excitation power supply that applies an alternating current with a superimposed direct current to the pair of coils; and a detection circuit that is connected to a connection point of the pair of coils. Unlike a conventional flux gate type geomagnetic sensor, it is not required to excite the core until the core is magnetically saturated, and it is therefore possible to reduce power consumption.

Abstract: A current sensor includes: two cores that configure closed magnetic circuits surrounding a conductor where a current to be measured flows and are arranged adjacent to each other; two coils that are wound respectively around the two cores and are connected in series to generate a magnetic flux in surrounding directions opposite to each other in the two cores; an excitation power supply that applies an alternating current with a superimposed direct current to the two coils; and a detection circuit that is connected to a connection point of the two coils. It is possible to obtain the current sensor being capable of high precision measurement up to high frequencies and also capable of reducing power consumption.

Abstract: An optical printer head has an array of lenses that project light emitted by an array of LEDs onto a charged photosensitive drum to form a latent image on the drum surface. A resin film adhered to the exposed surfaces of the lenses prevents chemical reaction between nitric acid, formed as a consequence of ozone produced during electric charging of the photosensitive drum, and alkali components on the surfaces of the lenses thereby preventing clouding of the lens surfaces and dimming of the projected light. The resin film has a thickness of 10 to 100 microns and may be formed of polyvinyl chloride, polyethylene terephthalate or polymethyl meta acrylate.

Abstract: An information processing apparatus may be implemented as a route navigator, which uses a route navigation method and a computer program product. A processing circuit is used to calculate respective passage frequencies of passageway segments in a passage history. The processing circuit then selects a navigation route to a destination, includes at least one passageway segment with a passage frequency that is a low or zero passage frequency.

Abstract: Flip-flop memory cells are connected to a pair of bit lines and respectively to word lines. A word line driver outputs a word line selection pulse to one of the word lines in a word line selection period. A write circuit gives a potential difference corresponding to input data to the pair of bit lines after a start of the word line selection period. In a first operation mode, the potential difference of the pair of bit lines is reset in the word line selection period, and in the second mode, the potential difference of the pair of bit lines is reset after the word line selection period.

Abstract: Flip-flop memory cells are connected to a pair of bit lines and respectively to word lines. A word line driver outputs a word line selection pulse to one of the word lines in a word line selection period. A write circuit gives a potential difference corresponding to input data to the pair of bit lines after a start of the word line selection period. In a first operation mode, the potential difference of the pair of bit lines is reset in the word line selection period, and in the second mode, the potential difference of the pair of bit lines is reset after the word line selection period.

Abstract: A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.

Abstract: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.

Abstract: A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.

Abstract: During a write cycle, a selected write-word-line driver drives the corresponding write word line such that the potential of the corresponding write word line is lower in a first period as a predetermined period after an initiation of the write cycle than in a second period as a predetermined period after the first period, and sense amplifiers amplify the potentials of the corresponding write bit lines in the first period.

Abstract: In a semiconductor memory device including memory cells each having two inverters connected in a cross-coupled configuration to hold High data and Low data as a pair and two access transistors, a plurality of word lines, and a plurality of bit lines, the potential of the selected one of the plurality of word lines is controlled to be lower than a potential obtained by adding up the potential of one of Low-data-holding power sources each for holding the Low data at any time other than during a read operation and the threshold voltage of each of the access transistors.

Abstract: A functional sheet is coated with physically vapor-deposited film including titanium oxide and other metallic oxides for making the film transparent so color and pattern on the fiber sheet are visible, providing electric conductivity to the film, improving the productivity of vapor deposition and enabling selective blocking of infrared and ultraviolet radiation.

Abstract: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.