Patents by Inventor Toshikazu Wakabayashi

Toshikazu Wakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100134466
    Abstract: Protective layer of front plate of the plasma display panel is formed of base protective layer and particle layer. Base protective layer is a thin film containing metal oxide. Particle layer is formed in a manner that aggregated particles of a plurality of magnesium-oxide single-crystal particles are stuck on base protective layer. The panel driving circuit drives the panel in a manner that an initializing discharge for forming wall charge is generated in a first subfield of the plurality of subfields, and an address discharge for erasing wall charge is generated in an address period of the plurality of subfields.
    Type: Application
    Filed: April 14, 2009
    Publication date: June 3, 2010
    Inventors: Mitsuhiro Murata, Kaname Mizokami, Toshikazu Wakabayashi
  • Publication number: 20100134453
    Abstract: Protective layer (26) of front plate (20) of a plasma display panel has base protective layer (26a) and particle layer (26b). Base protective layer (26a) is formed of a thin film of metal oxide containing at least one of magnesium oxide, strontium oxide, calcium oxide, and barium oxide. Particle layer (26b) is formed by sticking, to base protective layer (26a), single crystal particles (27) of magnesium oxide having an NaCl crystal structure that is surrounded by a specified two-type orientation face formed of (100) face and (111) face or a specified three-type orientation face formed of (100) face, (110) face, and (111) face. The panel driving circuit drives the panel while temporally disposing the subfields so that the luminance weight monotonically decreases from a subfield in which an all-cell initializing operation is performed to the subfield immediately before the subfield in which its next all-cell initializing operation is performed.
    Type: Application
    Filed: April 14, 2009
    Publication date: June 3, 2010
    Inventors: Mitsuhiro Murata, Yusuke Fukui, Toshikazu Wakabayashi, Hiroshi Asano
  • Publication number: 20100134455
    Abstract: In a plasma display panel, protective layer of front plate has base protective layer and particle layer. The base protective layer is formed of a thin film of a metal oxide containing at least one of magnesium oxide, strontium oxide, calcium oxide, and barium oxide. The particle layer is formed by sticking, to base protective layer, single-crystal particles of magnesium that have an NaCl crystal structure surrounded by specified two type orientation faces of a (100) face and a (111) face, or by specified three type orientation faces of a (100) face, a (110) face, and a (111) face. A panel driving circuit drives the panel in a manner that an initializing discharge for forming wall charge is caused in the first subfield of a plurality of subfields, and an address discharge for erasing the wall charge is caused in address periods of the plurality of subfields.
    Type: Application
    Filed: April 14, 2009
    Publication date: June 3, 2010
    Inventors: Mitsuhiro Murata, Yusuke Fukui, Toshikazu Wakabayashi, Hiroshi Asano
  • Publication number: 20100118015
    Abstract: Protective layer of a plasma display panel has base protective layer and particle layer. Base protective layer is formed of a thin film of metal oxide containing at least one of magnesium oxide, strontium oxide, calcium oxide, and barium oxide. Particle layer is formed by sticking, to base protective layer, single crystal particles of magnesium oxide where the peak at 200 to 300 nm is two or more times that at 300 to 550 nm in a cathode luminescence emission spectrum. The panel driving circuit causes initializing discharge for producing wall charge in the first subfield, of a plurality of subfields, causes address discharge for erasing wall charge in address periods of the plurality of subfields, and drives the panel.
    Type: Application
    Filed: April 14, 2009
    Publication date: May 13, 2010
    Inventors: Mitsuhiro Murata, Takuji Tsujita, Toshikazu Wakabayashi, Hiroshi Asano, Masaharu Terauchi
  • Publication number: 20100118004
    Abstract: A protective layer of a plasma display panel has a base protective layer formed of a thin film of a metal oxide, and a particle layer. The particle layer is formed by sticking, to the base protective layer, single-crystal particles of magnesium oxide such that the emission intensity of a peak at 200 nm to 300 nm is at least twice the emission intensity of a peak at 300 nm to 550 nm in an emission spectrum of cathode luminescence light emission. A panel driving circuit drives the panel in a manner that a second subfield group having a plurality of subfields is temporally disposed after a first subfield group having a plurality of subfields to form one field period. Each subfield of the first subfield group has initializing period (Ti), address period (Tw) for forming wall charge to cause a sustain discharge, and sustain period (Ts). Each subfield of the second subfield group has address period (Tw) for erasing wall charge necessary for causing a sustain discharge, and sustain period (Ts).
    Type: Application
    Filed: April 14, 2009
    Publication date: May 13, 2010
    Inventors: Mitsuhiro Murata, Takuji Tsujita, Toshikazu Wakabayashi, Hiroshi Asano, Masaharu Terauchi
  • Publication number: 20100118009
    Abstract: In the case of driving a plasma display panel for one field using a plurality of sub-fields each having a reset period in which reset discharge is generated in a discharge cell, an address period in which address discharge is generated in the discharge cell, and a sustain period in which sustain discharge is generated in the discharge cell, in a former period of the reset period, a rising ramp waveform voltage is applied to the scan electrodes, and a first voltage (Ve1) is applied to the sustain electrodes, and in a latter period of the reset period, a falling ramp waveform voltage is applied to the scan electrodes, and a second voltage (Ve2) higher than the first voltage (Ve1), a rising ramp waveform voltage rising from the second voltage (Ve2) to a third voltage (Ve3) higher than the second voltage (Ve2), and the third voltage (Ve3) are sequentially applied to the sustain electrodes.
    Type: Application
    Filed: November 17, 2008
    Publication date: May 13, 2010
    Inventors: Masumi Izuchi, Toshikazu Wakabayashi
  • Publication number: 20100109984
    Abstract: Protective layer of front plate of the plasma display panel is formed of base protective layer and particle layer. Base protective layer is a thin film of metal oxide containing at least one of magnesium oxide, strontium oxide, calcium oxide, and barium oxide. Particle layer is formed in a manner that single-crystal particles of magnesium oxide having a peak of emission intensity at 200-300 nm two times or higher than another peak of emission intensity at 300-550 nm in the emission spectrum in cathode luminescence emission are stuck on base protective layer. The panel driving circuit drives the panel with a subfield structure in which the subfields are temporally disposed so that magnitude of luminance weight has monotonous decrease from a subfield where the all-cell initializing operation is performed to a subfield where the next all-cell initializing operation is performed.
    Type: Application
    Filed: April 13, 2009
    Publication date: May 6, 2010
    Inventors: Mitsuhiro Murata, Takuji Tsujita, Toshikazu Wakabayashi, Hiroshi Asano, Masaharu Terauchi
  • Publication number: 20100085278
    Abstract: In a plasma display panel, protective layer of front plate has base protective layer and particle layer. The base protective layer is formed of a thin film containing magnesium oxide. The particle layer is formed by sticking, to base protective layer, agglomerated particles in which a plurality of single-crystal particles of magnesium oxide are agglomerated. A panel driving circuit drives the panel in a manner that subfields are temporally disposed so that the luminance weight is monotonically decreased from the subfield in which an all-cell initializing operation is performed to the subfield immediately preceding the subfield in which the next all-cell initializing operation is performed.
    Type: Application
    Filed: April 13, 2009
    Publication date: April 8, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Mitsuhiro Murata, Kaname Mizokami, Toshikazu Wakabayashi
  • Publication number: 20090244053
    Abstract: An object of the present invention is to provide a method for driving a plasma display panel capable of further reducing an address error to realize satisfactory image quality, and a plasma display apparatus.
    Type: Application
    Filed: June 6, 2007
    Publication date: October 1, 2009
    Inventors: Keiji Akamatsu, Toshikazu Wakabayashi, Yasuhiro Arai, Mitsuhiro Murata
  • Publication number: 20090201319
    Abstract: The aim is to improve the display capability of a PDP at lower gray scale levels by driving the PDP in a manner to adjust the luminance of Gray Scale 1 to an appropriate level. According to the drive method, one TV field is divided into a plurality of subfields SF 1, SF 2 . . . each having a reset period, an address period, and a sustain period. During the address period of SF 1, the sustain electrodes are held at a voltage (potential) Ve1. During the address period in SF 2 and the subsequent subfields, the sustain electrodes are held at a voltage (Ve+Ve2) The voltage Ve1 is higher than the ground voltage and lower than the voltage (Ve+Ve2).
    Type: Application
    Filed: September 18, 2007
    Publication date: August 13, 2009
    Inventors: Hiroyasu Makino, Toshikazu Wakabayashi, Hideki Ohmae
  • Publication number: 20090079720
    Abstract: An object of the present invention is to display an image with a good image quality when driving a PDP, by stabilizing an initialization operation to suppress a false discharge when a writing operation is performed. Therefore, in a method of driving a PDP of the present invention, one TV field is composed of a plurality of subfields each including an initialization period (31), a writing period (32), a sustain period (33), and an elimination period (34). When an immediately preceding subfield does not include the sustain period (33), a priming pulse (Vpr) is applied to address electrodes (D1 to Dm) prior to a ramp waveform part (S1) of an initialization pulse applied to scan electrodes (SCN1 to SCNn), after the writing operation ends. When the immediately preceding subfield includes the sustain period (33), the priming pulse (Vpr) is applied to the address electrodes (D1 to Dm) prior to the ramp waveform part (S1), after the sustain period ends.
    Type: Application
    Filed: May 1, 2007
    Publication date: March 26, 2009
    Inventors: Mitsuhiro Murata, Toshikazu Wakabayashi, Kyohei Yoshino
  • Patent number: 7477209
    Abstract: During each set-up period, wall charges of scan electrodes and sustain electrodes, between which sustain discharges were generated in the previous subfield, are adjusted, and parts toward the sustain electrodes of positive charges in the scan electrodes are replaced by negative charges and parts toward the scan electrodes of negative charges in the sustain electrodes are replaced by positive charges. During each address period, write pulses are applied to the scan electrodes to generate write discharges utilizing priming discharges between the scan electrodes and priming electrodes. During each sustain period, positive charges are accumulated in the entire surfaces of the scan electrodes and negative charges are accumulated in the entire surfaces of the sustain electrodes.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: January 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Toshikazu Wakabayashi, Hiroyuki Tachibana, Naoki Kosugi, Ryuichi Murai, Kenji Ogawa, Yoshimasa Horie
  • Patent number: 7432880
    Abstract: A method of driving a plasma display panel having display electrode pairs each one of which pairs is formed of a scan electrode and a sustain electrode. A priming electrode is placed in every other spaces between the display electrode pairs and in parallel with the display electrode pairs. An addressing period includes an odd-line addressing period in which an address operation is conducted to primary discharge cells having odd-number scan electrodes, an even-line addressing period in which an address operation is conducted to primary discharge cells having even-number scan electrodes. During the respective addressing periods, scan pulse voltage Va is applied to odd-number scan electrodes or even-number scan electrodes while priming pulse voltage Vp is applied, prior to the application of the scan pulse voltage, to a priming electrode adjacent to the scan electrode to which scan pulse voltage Va is to be applied, in order to generate a priming discharge between the priming electrodes and the data electrodes.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: October 7, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tachibana, Naoki Kosugi, Toshikazu Wakabayashi, Shigeyuki Okumura
  • Patent number: 7348937
    Abstract: Barrier ribs are disposed on a back substrate so as to separate main discharge cells and priming discharge cells, and the top parts of the barrier ribs are formed so as to abut on a front substrate. In a driving method, in an odd-numbered line writing time period, scan pulse Va is sequentially applied to odd-numbered scan electrode SCp and voltage Vq is applied to even-numbered sustain electrode SUp+1 to cause priming discharge between even-numbered sustain electrode SUp+1 and odd-numbered scan electrode SCp. In an even-numbered line writing time period, scan pulse Va is sequentially applied to even-numbered scan electrode SCp+1 and voltage Vq is applied to odd-numbered sustain electrode SUp to cause priming discharge between odd-numbered sustain electrode SUp and even-numbered scan electrode SCp+1.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: March 25, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tachibana, Jumpei Hashiguchi, Kenji Ogawa, Toshikazu Wakabayashi, Tomohiro Murakoso
  • Patent number: 7345655
    Abstract: Barrier ribs are disposed on a back substrate so as to separate main discharge cells formed of a display electrode pair and a data electrode which face each other and priming discharge cells formed of a clearance between two adjacent scan electrodes. The top parts of the barrier ribs are formed so as to abut on a front substrate. In a driving method, in an odd-numbered line writing time period, scan pulse Va is sequentially applied to odd-numbered scan electrode SCp and voltage Vq is applied to even-numbered scan electrode SCp+1 to cause priming discharge between scan electrode SCp+1 and odd-numbered scan electrode SCp. In an even-numbered line writing time period, scan pulse Va is sequentially applied to even-numbered scan electrode SCp+1 and voltage Vq is applied to odd-numbered scan electrode SCp to cause priming discharge between scan electrode SCp and even-numbered scan electrode SCp+1.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: March 18, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tachibana, Jumpei Hashiguchi, Kenji Ogawa, Toshikazu Wakabayashi, Tomohiro Murakoso
  • Patent number: 7342558
    Abstract: The initializing period of at least one of a plurality of sub-fields constituting one field is a selective initializing period for selectively initializing discharge cells in which a sustain discharge has occurred in the sustaining period of the preceding sub-field. In the sustaining period of the sub-field prior to the sub-field including the selective initializing period, voltage Vr is applied to a priming electrode (PRi) for causing a discharge between the priming electrode (PRi) and corresponding scan electrode (SCi) using the priming electrode (PRi) as a cathode.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: March 11, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tachibana, Naoki Kosugi, Toshikazu Wakabayashi, Yasuaki Muto
  • Patent number: 7298349
    Abstract: A method of driving a plasma display panel including a plurality of priming electrodes. The pulse width of scan pulses applied to some of a plurality of scan electrodes in which writing is performed and priming discharge is caused with the scanning of the scan electrodes is larger than the pulse width of scan pulses applied to the other scan electrodes in which writing is performed but no priming discharge is caused with the scanning of the scan electrodes.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: November 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tachibana, Toshikazu Wakabayashi, Shigeo Kigo, Nobuaki Nagao, Kenji Ogawa
  • Publication number: 20070222706
    Abstract: A method of driving a plasma display panel having display electrode pairs each one of which pairs is formed of a scan electrode and a sustain electrode. A priming electrode is placed in every other spaces between the display electrode pairs and in parallel with the display electrode pairs. An addressing period includes an odd-line addressing period in which an address operation is conducted to primary discharge cells having odd-number scan electrodes, an even-line addressing period in which an address operation is conducted to primary discharge cells having even-number scan electrodes. During the respective addressing periods, scan pulse voltage Va is applied to odd-number scan electrodes or even-number scan electrodes while priming pulse voltage Vp is applied, prior to the application of the scan pulse voltage, to a priming electrode adjacent to the scan electrode to which scan pulse voltage Va is to be applied, in order to generate a priming discharge between the priming electrodes and the data electrodes.
    Type: Application
    Filed: September 14, 2005
    Publication date: September 27, 2007
    Inventors: Hiroyuki Tachibana, Naoki Kosugi, Toshikazu Wakabayashi, Shigeyuki Okumura
  • Publication number: 20070109223
    Abstract: During each set-up period, wall charges of scan electrodes and sustain electrodes, between which sustain discharges were generated in the previous subfield, are adjusted, and parts toward the sustain electrodes of positive charges in the scan electrodes are replaced by negative charges and parts toward the scan electrodes of negative charges in the sustain electrodes are replaced by positive charges. During each address period, write pulses are applied to the scan electrodes to generate write discharges utilizing priming discharges between the scan electrodes and priming electrodes. During each sustain period, positive charges are accumulated in the entire surfaces of the scan electrodes and negative charges are accumulated in the entire surfaces of the sustain electrodes.
    Type: Application
    Filed: June 23, 2004
    Publication date: May 17, 2007
    Inventors: Toshikazu Wakabayashi, Hiroyuki Tachibana, Naoki Kosugi, Ryuichi Murai, Kenji Ogawa, Yoshimasa Horie
  • Patent number: 7176852
    Abstract: A front substrate contains a plurality of scan electrodes and sustain electrodes. Two strips of scan electrodes and two strips of sustain electrodes are alternately disposed on the substrate. In addition, a plurality of auxiliary scan electrodes is disposed on the front substrate so as to be parallel to the scan electrodes. On the back substrate, a plurality of priming electrodes is disposed parallel to the scan electrodes. Each auxiliary scan electrode has electrical connections to the scan electrode that performs scanning earlier than the scan electrode adjacent to each auxiliary scan electrode. With the structure above, a priming discharge occurs between the auxiliary scan electrodes and the priming electrodes.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tachibana, Naoki Kosugi, Toshikazu Wakabayashi