Patents by Inventor Toshimi Nakamura

Toshimi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935865
    Abstract: A method for producing a semiconductor package, capable of effectively suppressing contamination of a chemical liquid and unintended peeling-off of a reinforcing sheet, is provided. This method includes providing a tacky sheet including a substrate sheet, and a soluble tacky layer and a banking tacky layer on at least one surface of the substrate sheet; making a first laminate including a redistribution layer; using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the tacky layer therebetween; peeling off the first support substrate, pretreating the resulting third laminate; mounting a semiconductor chip on a pretreated surface of the redistribution layer; immersing the third laminate in a solution to dissolve or soften the tacky layer; and peeling off the second support substrate in a state where the tacky layer is dissolved or softened.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 19, 2024
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Tetsuro Sato
  • Publication number: 20240080990
    Abstract: There is provided a wiring substrate whose mechanical strength, water resistance, humidity resistance, and product yield can be improved. This wiring substrate includes a device region in which a main wiring pattern composed of a metal layer is embedded in an insulating layer; a peripheral region which surrounds a periphery of the device region and in which a dummy wiring pattern composed of a metal layer is embedded in an insulating layer; and an insulating boundary region interposed between the device region and the peripheral region, composed of an insulating layer. The insulating boundary region has a winding shape in which it is possible to draw a virtual straight line alternately traversing the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulating boundary region, parallel to an inscribed line of at least one side of an outer edge of the device region.
    Type: Application
    Filed: December 10, 2021
    Publication date: March 7, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi NAKAMURA, Mikiko KOMIYA, Yoshinori MATSUURA
  • Publication number: 20240034670
    Abstract: There is provided a carrier-attached metal foil in which the metal layer is less likely to be released at the ends of the carrier-attached metal foil or in the cutting place(s) of a downsized carrier-attached metal foil, and moreover a decrease in the strength of the carrier is effectively suppressed. This carrier-attached metal foil includes a carrier; a release layer provided on the carrier; and a metal layer having a thickness of 0.01 ?m or more and 4.0 ?m or less provided on the release layer. The carrier has a flat region having a developed interfacial area ratio Sdr of less than 5%, and an uneven region having a developed interfacial area ratio Sdr of 5% or more and 39% or less, on at least a surface on the metal layer side, and the uneven region is provided in a linear pattern surrounding the flat region.
    Type: Application
    Filed: November 29, 2021
    Publication date: February 1, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi NAKAMURA, Mikiko KOMIYA, Yoshinori MATSUURA
  • Patent number: 11876070
    Abstract: A method for producing a semiconductor package, capable of suppressing damage of a device, and dissolving or softening a tacky layer quickly to peel off a reinforcing sheet, is provided. This method includes: providing a tacky sheet including a soluble tacky layer, making a first laminate, obtaining a second laminate having a second support substrate bonded to the first laminate, peeling off a first support substrate to obtain a third laminate, mounting a semiconductor chip thereon to obtain a fourth laminate, sealing a right end surface and a left end surface of the fourth laminate with sealing members and immersing a lower end surface of the fourth laminate selectively in a solution, giving a pressure difference between an inner space and the solution to allow the solution to penetrate into the internal space and dissolve or soften the soluble tacky layer, and peeling off the second support substrate.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: January 16, 2024
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Tetsuro Sato
  • Patent number: 11756845
    Abstract: A glass carrier-attached copper foil is provided that can achieve a desired circuit mounting board that reduces separation of a copper layer at the cut edge even if the copper foil is downsized to dimensions enabling mount of a circuit, and has an intended circuit pattern with a fine pitch. The glass carrier-attached copper foil includes a glass carrier, a release layer, and a copper layer with a thickness of 0.1 to 3.0 ?m. The glass carrier has, at least on its surface having the copper layer thereon, a plurality of flat regions each having a maximum height Rz of less than 1.0 ?m as measured in accordance with JIS B 0601-2001 and a rough region having a maximum height Rz of 1.0 to 30.0 ?m as measured in accordance with JIS B 0601-2001. The rough region has a pattern of lines that define the flat regions.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 12, 2023
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Takenori Yanai, Toshimi Nakamura
  • Patent number: 11527415
    Abstract: There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 13, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Tetsuro Sato, Takenori Yanai, Toshimi Nakamura
  • Patent number: 11525073
    Abstract: There is a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween, wherein an unoccupied region without the soluble adhesive layer is provided within a facing area where the reinforcing sheet faces the multilayer laminate; allowing a liquid capable of dissolving the soluble adhesive layer to infiltrate the unoccupied region to dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced to generate no large local warpage, thereby improving the reliable connection and the surface flatness (coplanarity) of the multilayer wiring layer. The used reinforcing sheet can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 13, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Tetsuro Sato, Toshimi Nakamura, Takenori Yanai
  • Publication number: 20220223456
    Abstract: Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development.
    Type: Application
    Filed: May 18, 2020
    Publication date: July 14, 2022
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Toshimi NAKAMURA
  • Patent number: 11317522
    Abstract: Provided is a method of manufacturing a circuit board involves: preparing a composite laminate including a support, a release layer, and a multilayered circuit board; disposing the composite laminate on a stage such that one face of the composite laminate is put into tight contact with the stage; and releasing the support or the multilayered circuit board from the release layer such that the support or the multilayered circuit board forms a convex face with a curvature radius of 200 to 5000 mm while the face of the composite laminate is kept in tight contact with the stage. The method according to the present invention can prevent the occurrences of defects, for example, breaking in the support and cracking and wire disconnections in the multilayered circuit board in manufacturing of circuit boards, such as coreless circuit boards, and ensure stable release of the support or the multilayered circuit board.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 26, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Yoshinori Matsuura
  • Publication number: 20210327848
    Abstract: A method for producing a semiconductor package, capable of effectively suppressing contamination of a chemical liquid and unintended peeling-off of a reinforcing sheet, is provided. This method includes providing a tacky sheet including a substrate sheet, and a soluble tacky layer and a banking tacky layer on at least one surface of the substrate sheet; making a first laminate including a redistribution layer; using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the tacky layer therebetween; peeling off the first support substrate, pretreating the resulting third laminate; mounting a semiconductor chip on a pretreated surface of the redistribution layer; immersing the third laminate in a solution to dissolve or soften the tacky layer; and peeling off the second support substrate in a state where the tacky layer is dissolved or softened.
    Type: Application
    Filed: November 11, 2019
    Publication date: October 21, 2021
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi NAKAMURA, Tetsuro SATO
  • Publication number: 20210327847
    Abstract: A method for producing a semiconductor package, capable of suppressing damage of a device, and dissolving or softening a tacky layer quickly to peel off a reinforcing sheet, is provided. This method includes: providing a tacky sheet including a soluble tacky layer, making a first laminate, obtaining a second laminate having a second support substrate bonded to the first laminate, peeling off a first support substrate to obtain a third laminate, mounting a semiconductor chip thereon to obtain a fourth laminate, sealing a right end surface and a left end surface of the fourth laminate with sealing members and immersing a lower end surface of the fourth laminate selectively in a solution, giving a pressure difference between an inner space and the solution to allow the solution to penetrate into the internal space and dissolve or soften the soluble tacky layer, and peeling off the second support substrate.
    Type: Application
    Filed: November 11, 2019
    Publication date: October 21, 2021
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi NAKAMURA, Tetsuro SATO
  • Publication number: 20210274650
    Abstract: There is provided a laminate that can suppress the warpage of a laminated product when used for the manufacture of the laminated product. This laminate includes a float glass substrate having a top surface and a bottom surface; and a metal layer provided on the top surface side of the float glass substrate.
    Type: Application
    Filed: May 11, 2021
    Publication date: September 2, 2021
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Rintaro ISHII, Toshimi NAKAMURA, Yoshinori MATSUURA
  • Patent number: 11071214
    Abstract: Provided is a method of manufacturing a multilayer wiring board, in which electrical inspection can be performed with accurate probing while warpage of a multilayer laminate is reduced. This method includes providing a laminated sheet including a first support, a first release layer and a metal layer; alternately stacking wiring layers and insulating layers on a surface of the metal layer, wherein an n-th wiring layer being the uppermost layer includes an n-th connection pad; bonding a second support having an opening on a surface, remote from the laminated sheet, of the multilayer laminate with a second release layer therebetween such that at least a part of the n-th connection pad is disposed within the opening; releasing the first support from the reinforced multilayer laminate at the first release layer; and putting conductors into contact with the n-th connection pads of the reinforced multilayer laminate to perform electrical inspection.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 20, 2021
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Yasuhiro Seto, Toshimi Nakamura
  • Publication number: 20200411396
    Abstract: A glass carrier-attached copper foil is provided that can achieve a desired circuit mounting board that reduces separation of a copper layer at the cut edge even if the copper foil is downsized to dimensions enabling mount of a circuit, and has an intended circuit pattern with a fine pitch. The glass carrier-attached copper foil includes a glass carrier, a release layer, and a copper layer with a thickness of 0.1 to 3.0 ?m. The glass carrier has, at least on its surface having the copper layer thereon, a plurality of flat regions each having a maximum height Rz of less than 1.0 ?m as measured in accordance with JIS B 0601-2001 and a rough region having a maximum height Rz of 1.0 to 30.0 ?m as measured in accordance with JIS B 0601-2001. The rough region has a pattern of lines that define the flat regions.
    Type: Application
    Filed: February 13, 2019
    Publication date: December 31, 2020
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Takenori YANAI, Toshimi NAKAMURA
  • Patent number: 10840180
    Abstract: A method of manufacturing a multilayer wiring board is disclosed, the method being capable of reinforcing the multilayer wiring layer and thereby improving the reliability of connection and the flatness on the surface of the multilayer wiring layer. The method includes providing a laminated sheet having a substrate, a first release layer and a metal layer; forming a first wiring layer on the metal layer; alternately stacking insulating layers and wiring layers on the laminated sheet on which the first wiring layer is formed to give a laminate provided with a multilayer wiring layer; stacking a reinforcing sheet on the laminate provided with the multilayer wiring layer at the side opposite to the laminate sheet, while interposing the second release layer; separating the substrate from the metal layer; and separating the reinforcing sheet from the laminate provided with the multilayer wiring layer to give the multilayer wiring board.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 17, 2020
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Takenori Yanai, Toshimi Nakamura
  • Publication number: 20200113066
    Abstract: Provided is a method of manufacturing a circuit board involves: preparing a composite laminate including a support, a release layer, and a multilayered circuit board; disposing the composite laminate on a stage such that one face of the composite laminate is put into tight contact with the stage; and releasing the support or the multilayered circuit board from the release layer such that the support or the multilayered circuit board forms a convex face with a curvature radius of 200 to 5000 mm while the face of the composite laminate is kept in tight contact with the stage. The method according to the present invention can prevent the occurrences of defects, for example, breaking in the support and cracking and wire disconnections in the multilayered circuit board in manufacturing of circuit boards, such as coreless circuit boards, and ensure stable release of the support or the multilayered circuit board.
    Type: Application
    Filed: March 9, 2018
    Publication date: April 9, 2020
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi NAKAMURA, Yoshinori MATSUURA
  • Publication number: 20200045829
    Abstract: A method of manufacturing a multilayer wiring board is disclosed, the method being capable of reinforcing the multilayer wiring layer and thereby improving the reliability of connection and the flatness on the surface of the multilayer wiring layer. The method includes providing a laminated sheet having a substrate, a first release layer and a metal layer; forming a first wiring layer on the metal layer; alternately stacking insulating layers and wiring layers on the laminated sheet on which the first wiring layer is formed to give a laminate provided with a multilayer wiring layer; stacking a reinforcing sheet on the laminate provided with the multilayer wiring layer at the side opposite to the laminate sheet, while interposing the second release layer; separating the substrate from the metal layer; and separating the reinforcing sheet from the laminate provided with the multilayer wiring layer to give the multilayer wiring board.
    Type: Application
    Filed: October 6, 2016
    Publication date: February 6, 2020
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Takenori YANAI, Toshimi NAKAMURA
  • Publication number: 20200045830
    Abstract: A method of manufacturing a multilayer wiring board is disclosed, the method being capable of separating a substrate without large local warpage of the multilayer wiring layer and thereby improving the reliability of connection in the multilayer wiring layer. This method includes providing a laminated sheet having, in sequence, a substrate, a first release layer and a metal layer; forming a first wiring layer on the metal layer; alternately stacking insulating layers and wiring layers on the laminated sheet on which the first wiring layer is formed to give a laminate provided with a multilayer wiring layer; stacking a reinforcing sheet on the laminate provided with the multilayer wiring layer while interposing a second release layer; separating the substrate from the metal layer; and separating the reinforcing sheet from the laminate provided with the multilayer wiring layer to give the multilayer wiring board.
    Type: Application
    Filed: October 6, 2016
    Publication date: February 6, 2020
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Takenori YANAI, Toshimi NAKAMURA
  • Publication number: 20190378727
    Abstract: There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
    Type: Application
    Filed: November 24, 2017
    Publication date: December 12, 2019
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Tetsuro SATO, Takenori YANAI, Toshimi NAKAMURA
  • Publication number: 20190378728
    Abstract: There is a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween, wherein an unoccupied region without the soluble adhesive layer is provided within a facing area where the reinforcing sheet faces the multilayer laminate; allowing a liquid capable of dissolving the soluble adhesive layer to infiltrate the unoccupied region to dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced to generate no large local warpage, thereby improving the reliable connection and the surface flatness (coplanarity) of the multilayer wiring layer. The used reinforcing sheet can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
    Type: Application
    Filed: November 24, 2017
    Publication date: December 12, 2019
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Tetsuro SATO, Toshimi NAKAMURA, Takenori YANAI