Patents by Inventor Toshimitsu Taniguchi
Toshimitsu Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230215945Abstract: In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.Type: ApplicationFiled: March 10, 2023Publication date: July 6, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi OGURA, Takashi HIROSHIMA, Toshimitsu TANIGUCHI, Peter A. BURKE
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Patent number: 11605734Abstract: In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.Type: GrantFiled: October 25, 2021Date of Patent: March 14, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Ogura, Takashi Hiroshima, Toshimitsu Taniguchi, Peter A. Burke
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Publication number: 20220045209Abstract: In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.Type: ApplicationFiled: October 25, 2021Publication date: February 10, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi OGURA, Takashi HIROSHIMA, Toshimitsu TANIGUCHI, Peter A. BURKE
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Patent number: 11227928Abstract: In a general aspect, a trench-gate field-effect transistor can include an active region and a termination region. The termination region can include a structure where a portion in which formation of a PN junction is prevented (e.g., a termination extension and one or more semiconductor mesas) is overlapped with a portion of the trench-FET that includes a boundary (edge, etc.) between trenches (or portions of trenches) lined with only shield (thick oxide) and trenches lined with a stepped-shield dielectric (SSO) structure (e.g., shield dielectric and gate dielectric). That boundary can be referred to an SSO edge. Prevention of PN junction formation (e.g., during a channel and/or body implant for the trench-FET), in the disclosed approaches, can be accomplished using a polysilicon layer to block formation of, e.g., a p-type layer, in a semiconductor substrate (e.g., an n-type semiconductor region, epitaxial layer, etc.).Type: GrantFiled: October 1, 2020Date of Patent: January 18, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Ogura, Takashi Hiroshima, Toshimitsu Taniguchi
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Publication number: 20220013647Abstract: In a general aspect, a trench-gate field-effect transistor can include an active region and a termination region. The termination region can include a structure where a portion in which formation of a PN junction is prevented (e.g., a termination extension and one or more semiconductor mesas) is overlapped with a portion of the trench-FET that includes a boundary (edge, etc.) between trenches (or portions of trenches) lined with only shield (thick oxide) and trenches lined with a stepped-shield dielectric (SSO) structure (e.g., shield dielectric and gate dielectric). That boundary can be referred to an SSO edge. Prevention of PN junction formation (e.g., during a channel and/or body implant for the trench-FET), in the disclosed approaches, can be accomplished using a polysilicon layer to block formation of, e.g., a p-type layer, in a semiconductor substrate, e.g., an n-type semiconductor region, epitaxial layer, etc.).Type: ApplicationFiled: October 1, 2020Publication date: January 13, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi OGURA, Takashi HIROSHIMA, Toshimitsu TANIGUCHI
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Patent number: 11158734Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus includes a plurality of body region segments of a second conductivity type disposed in the side of the mesa region. The plurality of body region segments define an alternating pattern with the plurality of source region segments along the side of the mesa region.Type: GrantFiled: July 16, 2019Date of Patent: October 26, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Ogura, Takashi Hiroshima, Toshimitsu Taniguchi, Peter A. Burke
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Publication number: 20200312996Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus includes a plurality of body region segments of a second conductivity type disposed in the side of the mesa region. The plurality of body region segments define an alternating pattern with the plurality of source region segments along the side of the mesa region.Type: ApplicationFiled: July 16, 2019Publication date: October 1, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi OGURA, Takashi HIROSHIMA, Toshimitsu TANIGUCHI, Peter A. BURKE
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Patent number: 10340372Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.Type: GrantFiled: April 3, 2018Date of Patent: July 2, 2019Assignee: Semiconductor Components Industries, LLCInventors: Takashi Ogura, Mitsuru Soma, Dean E. Probst, Takashi Hiroshima, Peter A. Burke, Toshimitsu Taniguchi
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Publication number: 20190189788Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.Type: ApplicationFiled: April 3, 2018Publication date: June 20, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi OGURA, Mitsuru SOMA, Dean E. PROBST, Takashi HIROSHIMA, Peter A. BURKE, Toshimitsu TANIGUCHI
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Publication number: 20130187158Abstract: The invention prevents a short circuit between bonding wires, between device pads, or between the bonding wire and the device pad due to a cut residue portion of a scribe TEG pad coming off from an end portion of a semiconductor chip. A scribe TEG pad on a semiconductor wafer is formed of a plurality of rectangular pads each extending on a scribe line toward a device forming region. The semiconductor wafer is divided into semiconductor chips by dicing. At this time, the length of each of cut residue portions of the scribe TEG pad remaining on an end portion of the semiconductor chip is shorter than an interval between the end portions of openings of a passivation film on adjacent device pads.Type: ApplicationFiled: January 18, 2013Publication date: July 25, 2013Inventor: Toshimitsu TANIGUCHI
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Patent number: 7372164Abstract: A semiconductor forming transistors on a semiconductor substrate includes a low concentration source/drain region formed in the semiconductor substrate, a high concentration source/drain region formed in the source/drain region, a gate electrode formed on the substrate through gate oxide film, a P type body region formed under the gate electrode and placed between the source/drain regions and, plug contact portions contacting the source/drain region and arranged in plural, and a source/drain electrode connecting to the source/drain region with contact through the contact portions.Type: GrantFiled: February 2, 2005Date of Patent: May 13, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshinori Hino, Naoei Takeishi, Toshimitsu Taniguchi
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Patent number: 7224023Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.Type: GrantFiled: March 23, 2004Date of Patent: May 29, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Toshimitsu Taniguchi, Takashi Arai, Masashige Aoyama
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Patent number: 7109538Abstract: A nonvolatile semiconductor memory device includes a plurality of memory transistors, a plurality of insulating layers disposed over the transistors, and a plurality of metal layers. Each of the metal layers is disposed on one of the insulating layers. The device also includes a plurality of metal plugs disposed over corresponding memory transistors. Each of the metal plugs filling in a contact hole formed in one of the insulating layers and electrically connecting the metal layers disposed on a top side and a bottom side of the corresponding insulating layer. A top metal layer of the plurality of metal layers is configured to provide bit lines that correspond to the memory transistors, the metal plugs are vertically aligned, and one of the insulating layers is configured so that whether one of the memory transistors is connected to a corresponding bit line is determined by whether a metal plug corresponding to the memory transistor exists in the insulating layer.Type: GrantFiled: October 30, 2003Date of Patent: September 19, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Shuichi Takahashi, Fumiko Shikakura, Shinya Mori, Junji Yamada, Yutaka Yamada, Toshimitsu Taniguchi
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Patent number: 7045866Abstract: This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data “1” or “0” in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.Type: GrantFiled: November 5, 2004Date of Patent: May 16, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Toshimitsu Taniguchi, Toshiyuki Ohkoda
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Patent number: 7022575Abstract: An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.Type: GrantFiled: October 28, 2004Date of Patent: April 4, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Katsuhiko Iizuka, Kazuo Okada, Tomonori Mori, Hiroyuki Dobashi, Hiroyuki Suzuki, Takayoshi Honda, Toshimitsu Taniguchi
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Patent number: 6924534Abstract: The invention is directed to reducing of the number of steps in a BiCMOS process. A first N-well 3A and a second N-well 3B are formed deeply on a surface of a P-type semiconductor substrate. A first P-well 4A is formed in the first N-well 3A, and an N-channel MOS transistor is formed in the first P-well 4A. The second N-well 3B is used as a collector of a vertical NPN bipolar transistor. A second P-well 4B is formed in the second N-well 3B. The second P-well 4B is formed simultaneously with the first P-well 4A. The second P-well 4B is used as a base of the vertical NPN bipolar transistor. An N+ emitter layer and a P+ base electrode layer of the vertical NPN bipolar transistor are formed on a surface of the second P-well 4B.Type: GrantFiled: April 2, 2004Date of Patent: August 2, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Kazutomo Goshima, Toshiyuki Ohkoda, Toshimitsu Taniguchi
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Publication number: 20050156250Abstract: A semiconductor forming transistors on a semiconductor substrate includes a low concentration source/drain region formed in the semiconductor substrate, a high concentration source/drain region formed in the source/drain region, a gate electrode formed on the substrate through gate oxide film, a P type body region formed under the gate electrode and placed between the source/drain regions and, plug contact portions contacting the source/drain region and arranged in plural, and a source/drain electrode connecting to the source/drain region with contact through the contact portions.Type: ApplicationFiled: February 2, 2005Publication date: July 21, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Yoshinori Hino, Naoei Takeishi, Toshimitsu Taniguchi
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Publication number: 20050151205Abstract: This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data “1” or “0” in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.Type: ApplicationFiled: November 5, 2004Publication date: July 14, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Toshimitsu Taniguchi, Toshiyuki Ohkoda
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Publication number: 20050136629Abstract: An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.Type: ApplicationFiled: October 28, 2004Publication date: June 23, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Katsuhiko Iizuka, Kazuo Okada, Tomonori Mori, Hiroyuki Dobashi, Hiroyuki Suzuki, Takayoshi Honda, Toshimitsu Taniguchi
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Publication number: 20050118765Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.Type: ApplicationFiled: March 23, 2004Publication date: June 2, 2005Applicant: Sanyo Eletric Co., Ltd.Inventors: Toshimitsu Taniguchi, Takashi Arai, Masashige Aoyama