Abstract: There is provided an apparatus and method for three-dimensional measurements by shining an object to be measured with plural laser beams while scanning. Even if the optical intensity of laser beams is weak, light disturbance is accurately separated to perform real-time three-dimensional measurement. A laser beam emitted from a laser source is separated into the plural beams of slit light with a predetermined angle at a hologram plate. These two beams are used for scanning and irradiating the object by a scanning mirror. These beams are reflected and read to determine whether or not an interval between these beams corresponds to the predetermined angle.

Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.

Abstract: An arithmetic circuit, which is retained by each pixel in a conventional image sensor, is shared by each column. Signal processing circuits of different configurations are provided on signal transmission paths in an upward direction and a downward direction of a vertical signal line for extracting an image signal from each pixel, whereby image output processing and arithmetic processing are performed completely separately by the different circuit blocks. Thus, image quality of an actual image is improved and optimum design for arithmetic processing is made possible. Specifically, an I-V converter circuit unit, a CDS circuit unit and the like are provided on the image output side. A current mirror circuit unit, an analog memory array unit, a comparator unit, a bias circuit unit, a data latch unit, an output data bus unit and the like are provided on the arithmetic processing side.

Abstract: In distance measuring equipment for measuring the shape of a three-dimensional object by using a light sectioning method, charges accumulated in two photodiodes PDA, PDB provided every unit pixel of a pixel portion are successively read out as signal current to vertical signal lines. In a signal processing portion provided every column, it is judged in a comparator which photodiode PDA or PDB outputs higher light intensity. Therefore, the high/low intensity relationship is reversed when a laser beam passes over a specific pixel through a scanning operation of the laser beam, and the comparison output of the comparator circuit is reversed, so that the passage of the laser light over the unit pixel can be detected.

Abstract: A latch-type sensing circuit comprising a first inverter and a second inverter, where at least the first inverter has a variable threshold value of logical inversion. The inverters can have two transistors, where each transistor can have source/drain regions, an channel forming region interposed between the source/drain region, and a floating electrode formed above the channel-forming region through a first insulating layer. There features result in a more simplified circuit configuration.

Abstract: A semiconductor nonvolatile memory device wherein memory transistors in which data is electrically programmed in units of pages by performing the data programming together for selected memory transistors of a sector selected in response to page program data in units of sectors are arranged in the form of a matrix, provided with a means for continuously inputting the page program data of a plurality of page areas in synchronization with a constant clock pulse and continuously performing the page programming according to the plurality of page program data.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A program-verify circuit for an electrically re-writable memory cell which has a floating gate and a control gate and permits storage of a ternary or higher multi-valued data, the program-verify circuit comprising (1) a variable threshold voltage field-effect transistor having a plurality of input gate electrodes, and (2) a latch circuit, wherein the latch circuit is connected to one source/drain region of the variable threshold voltage field-effect transistor and is to be connected to the memory cell through a bit line, one of the input gate electrodes of the variable threshold voltage field-effect transistor is to be connected to the memory cell through the bit line, and a potential for controlling the conduction/non-conduction state of the variable threshold voltage field-effect transistor is to be applied to the rest of the input gate electrodes.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A ferroelectric nonvolatile semiconductor memory using a ferroelectric film as a dielectric film between a floating gate and a control gate, wherein a write switching transistor is provided between the floating gate and the bit line so as to enable the application of any voltage to the ferroelectric film using the voltage applied to the control gate and the voltage applied to the bit line and thereby enabling writing by a low voltage.

Abstract: A silicon nitride film is deposited on a semiconductor substrate in a plasma generated with SiH.sub.4 and nitride gases by the application of high-frequency electric energy. An allowable range of ultraviolet radiation absorption rates of the silicon nitride film, and also an allowable range of inner stresses of the silicon nitride film are established. Levels of both the flow rate of the SiH.sub.4 gas and the high-frequency electric energy are determined so that the silicon nitride film will satisfy the allowable range of ultraviolet radiation absorption rates with a wide margin and the allowable range of inner stresses with a wide margin.