Patents by Inventor Toshinori Imai
Toshinori Imai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030153187Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: February 21, 2003Publication date: August 14, 2003Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20030109129Abstract: A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.Type: ApplicationFiled: December 27, 2002Publication date: June 12, 2003Inventors: Tatsuyuki Saito, Naofumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
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Publication number: 20030089928Abstract: Provided is a semiconductor device comprising a first interlayer insulating film formed over a semiconductor substrate and having a wiring trench; a wiring portion which has a first barrier metal layer formed over the side walls and bottom surface of said wiring trench, a first conductor layer formed over said first barrier metal layer so as to embed said wiring trench with said first conductor layer, and a capping barrier metal film formed over the surface of said first conductor layer; a second interlayer insulating film formed over said first interlayer insulating film and having a connecting hole; and a connecting portion which has a second barrier metal layer formed over the side walls and bottom surface of said connecting hole, and a second conductor layer formed over said second barrier metal layer so as to embed said connecting hole with said second conductor layer; wherein at a joint between said connecting portion and said wiring portion, at least either one of said second barrier metal layer or saiType: ApplicationFiled: November 15, 2002Publication date: May 15, 2003Inventors: Tatsuyuki Saito, Naofumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
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Patent number: 6561875Abstract: The apparatus and method for producing a substrate whose surface includes a metallic wire by polishing the substrate surface. A polishing liquid is supplied to a clearance between the substrate and the surface of a polishing pad. The polishing liquid includes an acid which dissolves the oxidized part of the substrate surface and is substantially free of solid abrasive powder. A relative movement is generated between the substrate surface and the polishing pad surface while the substrate surface is pressed against the polishing pad surface while the polishing liquid is supplied so that the dissolved oxidized part of the substrates surface can be removed from the substrate.Type: GrantFiled: April 26, 2000Date of Patent: May 13, 2003Assignee: Hitachi, Ltd.Inventors: Yoshio Homma, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai
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Publication number: 20030073317Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.Type: ApplicationFiled: November 19, 2002Publication date: April 17, 2003Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
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Patent number: 6531400Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: August 19, 2002Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20030045088Abstract: Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.Type: ApplicationFiled: July 16, 2002Publication date: March 6, 2003Applicant: Hitachi, Ltd.Inventors: Toshinori Imai, Tsuyoshi Fujiwara, Tomohiro Shiraishi, Hiroshi Ashihara, Masaaki Yoshida
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Patent number: 6509273Abstract: Problematic dishing and erosion in forming embedded metal interconnection by a chemical mechanical polishing (CMP) method are suppressed. Formation of embedded Cu interconnects 46a to 46e by chemical mechanical polishing of a Cu film 46 formed in interconnect trenches 40 to 44 is performed by abrasive-grain-free chemical mechanical polishing using a polishing liquid of an abrasive grain content less than 0.5 wt % (CMP of the first step); with-abrasive-grain chemical mechanical polishing using a polishing liquid of an abrasive grain content of 0.5 or more wt % (CMP of the second step); and selective chemical mechanical polishing using a polishing liquid to which an anticorrosive such as benzotriazole (BTA) is added (CMP of the third step).Type: GrantFiled: March 17, 2000Date of Patent: January 21, 2003Assignee: Hitachi, Ltd.Inventors: Toshinori Imai, Naofumi Ohashi, Yoshio Homma, Seiichi Kondo
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Publication number: 20030003713Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.Type: ApplicationFiled: August 26, 2002Publication date: January 2, 2003Applicant: Hitachi, Ltd.Inventors: Yoshio Homma, Seiichi Kondo, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada
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Publication number: 20020193051Abstract: In an apparatus and method for producing a substrate whose surface includes a metallic wire by polishing the substrate surface,Type: ApplicationFiled: August 8, 2002Publication date: December 19, 2002Applicant: Hitachi, Ltd.Inventors: Yoshio Homma, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai
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Publication number: 20020192967Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: August 19, 2002Publication date: December 19, 2002Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6495466Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.Type: GrantFiled: April 3, 2001Date of Patent: December 17, 2002Assignee: Hitachi Ltd.Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
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Patent number: 6458674Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the resurfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: January 18, 2002Date of Patent: October 1, 2002Assignee: Hitachi, Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20020058363Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: ApplicationFiled: January 18, 2002Publication date: May 16, 2002Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 6376345Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: July 20, 1999Date of Patent: April 23, 2002Assignee: Hitachi Ltd.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Publication number: 20020025605Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.Type: ApplicationFiled: October 17, 2001Publication date: February 28, 2002Applicant: Hitachi, Ltd.Inventors: Yoshio Homma, Seiichi Kondo, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada
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Patent number: 6326299Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.Type: GrantFiled: July 28, 1999Date of Patent: December 4, 2001Assignee: Hitachi, Ltd.Inventors: Yoshio Homma, Seiichi Kondo, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada
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Publication number: 20010045651Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.Type: ApplicationFiled: May 8, 2001Publication date: November 29, 2001Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
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Publication number: 20010034132Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.Type: ApplicationFiled: April 3, 2001Publication date: October 25, 2001Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
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Patent number: 6042647Abstract: In a nozzle system for feeding treatment liquid, a storage tank is equipped with a nozzle comprising an opening and a stopcock which opens and closes said opening. When the stopcock opens the opening, a predetermined amount of liquid developer is dropped from the tank onto a wafer through a narrow gap between the outer surface of the stopcock and the inner edge of the opening. Thereby, the large amount of the liquid developer can be discharged and diffused on the entire wafer surface for a short time. Besides, the liquid amount is controlled with ease, and damage to the wafer is reduced, which enables a high quality of the development.Type: GrantFiled: May 15, 1998Date of Patent: March 28, 2000Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Kazushi Kawakami, Toshinori Imai