Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.

Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract: To reduce a mounting area while securing a mounting strength of a semiconductor device, a power transistor includes a chip mounting portion, a semiconductor chip, a plurality of leads, and a sealing body. An outer lead portion in each of the plurality of leads includes a first portion protruding from a second side surface of the sealing body in a first direction, a second portion extending in a second direction intersecting with the first direction, and a third portion extending in a third direction intersecting with the second direction. Furthermore, a length of the third portion in the third direction of the outer lead portion is shorter than a length of the first portion in the first direction.

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.

Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.

Abstract: A semiconductor flat package device capable of attaining a favorable operation and ensuring a sufficient spreading quality of solder for the lead top end is provided. A semiconductor chip 1 is encapsulated by an encapsulation resin. At first, a lead is half-blanked on the side of the top end of the lead protruding from the encapsulation region in the direction from the soldering surface to the printed circuit board, thereby forming a half-blanked region. Then, a plating layer is formed to the half-blanked region of the lead. Then, the lead is cut from the upper end of the half-blanked region formed with the plating layer in the direction from the soldering surface. The half-blanked region and the lead cut region form the top end face of the lead which forms a pseudo-planar face. Thus, a plating layer of a sufficient area is formed stably to the top end face of the lead. As a result, a solder fillet of a sufficient height is formed stably at the top end face of the lead.

Abstract: In a semiconductor device including a semiconductor chip featuring opposite first and second principal faces, and side faces extending therebetween, a first electrode layer is formed on the first principal face, and a second electrode layer is formed on the second principal face. A first metal electrode terminal is electrically adhered to the first electrode layer so that a part of the first metal electrode terminal protrudes out of one of the side faces, and a second metal electrode terminal is electrically adhered to the second electrode layer so that a part of the second metal electrode terminal protrudes out of the one of the side faces of the semiconductor chip. The parts of the first and second metal electrode terminals have respective soldering faces which are perpendicular to the first and second principal faces, and are coplanar with each other.

Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.

Abstract: A lead frame structure includes: at least a die pad for mounting a semiconductor chip thereon; a plurality of suspension members mechanically connected with the die pad; and a plurality of supporting members. Each supporting member has a connection region mechanically connected with each of the plurality of suspension members for mechanically supporting the at least die pad via the plurality of suspension pins. The connection region of the supporting member has a penetrating opening portion which provides a mechanical flexibility to the connection region and which allows the connection region to be deformed toward the suspension member upon application of a tensile stress to the suspension member in a down-set process.

Abstract: In a semiconductor device including a semiconductor chip featuring opposite first and second principal faces, and side faces extending therebetween, a first electrode layer is formed on the first principal face, and a second electrode layer is formed on the second principal face. A first metal electrode terminal is electrically adhered to the first electrode layer so that a part of the first metal electrode terminal protrudes out of one of the side faces, and a second metal electrode terminal is electrically adhered to the second electrode layer so that a part of the second metal electrode terminal protrudes out of the one of the side faces of the semiconductor chip. The parts of the first and second metal electrode terminals have respective soldering faces which are perpendicular to the first and second principal faces, and are coplanar with each other.