Abstract: A reading part, in a first reset period PR1, holds reset transistors in all pixels in a conductive state and executes a first conversion gain reset readout processing HSR, stores an AD conversion code with respect to a first readout reset, signal HCGVRST in a memory part, then, in a transfer period PT1, holds the transfer transistors in all pixels in a conductive state to transfer the accumulated charges in photodiodes PD1 to FD1 to thereby execute a global shutter operation accumulating overflowed charges in storage capacitors CS1. The reading part, when reading each row, executes a first conversion gain signal readout processing, a second conversion gain signal readout processing, and a second conversion gain reset readout processing in order. Due to this, it becomes possible to realize digital pixels provided with a global shutter function at a small pixel pitch.

Abstract: A comparator in an AD conversion part performs, under the control of reading part, a first comparison processing outputting a digitized first comparison result signal with respect to a voltage signal corresponding to an overflow charge overflowing from a PD1 to an FD1 in an integration period and a second comparison processing outputting a digitized second comparison result signal with respect to a voltage signal corresponding to a accumulated charge of the PD1 transferred to the FD1 in a transfer period after the integration period and, in the first comparison processing, starts an AD conversion processing comparing the voltage signal of the output buffer part and the reference voltage and outputting the digitized comparison result signal with a delay from the starting time of the first comparison processing. The comparator lowers a power consumption and suppresses an influence of a dark current of the FD and deterioration of an image.

Abstract: A comparator in an AD conversion part, under the control of a reading part, performs a first comparison processing outputting a digitized first comparison result signal with respect to a voltage signal corresponding to an overflow charge overflowing from a PD1 to an FD1 in an integration period, and a second comparison processing outputting a digitized second comparison result signal with respect to a voltage signal corresponding to a accumulated charge of the PD1 transferred to the FD1 in a transfer period after the integration period and, in the first comparison processing, the period of the first comparison processing is divided into a plurality of sub periods and, in each of the sub periods, the comparator performs an AD conversion processing comparing the voltage signal of the output buffer part and the reference voltage and outputting the digitized comparison result signal.

Abstract: A pixel portion includes a first pixel array in which a plurality of photoelectric conversion reading parts of first pixels are arranged in a matrix, a holding part array in which a plurality of signal holding parts of first pixels are arranged in a matrix, and a second pixel array in which a plurality of photoelectric conversion reading parts of second pixels are arranged in a matrix, wherein, at the time of a rolling shutter mode, readout signals of the photoelectric conversion reading parts of the first pixels and the second pixels are immediately output to a first vertical signal line without following a bypass route and, at the time of a global shutter mode, held signals of the signal holding parts of the first pixels are output to a second vertical signal line. Due to this, a solid-state imaging device can prevent complication of the configuration.

Abstract: A comparator in an AD conversion part, under the control of a reading part, performs a first comparison processing outputting a digitized first comparison result signal with respect to a voltage signal corresponding to an overflow charge overflowing from a photodiode PD1 to FD1 in an integration period and performs a second comparison processing outputting a digitized second comparison result signal with respect to a voltage signal corresponding to an accumulated charge of the photodiode PD1 transferred to the FD1 after a transfer period after the integration period, and a signal processing part performs combinational processing applying FWC information and joining a first AD conversion transfer curve TC1 corresponding to the first comparison processing and a second AD conversion transfer curve TC2 corresponding to the second comparison processing. Thus, it is possible to smoothly switch (connect) a plurality of signals to be combined and to suppress deterioration of an image.

Abstract: An AD conversion part has a comparator for performing comparison processing comparing a voltage signal read out by a photoelectric converting and reading part and a reference voltage and outputting a digitalized comparison result signal, the comparator, under the control by a reading part, performs first comparison processing for outputting a digitalized first comparison result signal with respect to a voltage signal corresponding to an overflow charge overflowing from a photodiode PD1 to a floating diffusion FD1 in an integration period and second comparison processing for outputting a digitalized second comparison result signal with respect to a voltage signal corresponding to an accumulated charge of the photodiode PD1 transferred to the floating diffusion FD1 in a transfer period after the integration period. Due to this, it becomes possible to substantially realize a broader dynamic range and higher frame rate.

Abstract: A solid-state imaging device, in which a signal holding part can hold a signal with respect to a voltage signal corresponding to an accumulated charge in a photoelectric conversion element of a photodiode PD1 which is transferred to an output node of a floating diffusion FD1 in a transfer period after an integration period and a signal with respect to a voltage signal corresponding to an overflow charge overflowing to the output node of the floating diffusion FD1 from at least the photodiode PD1 in any period among the photoelectric conversion element of the photodiode PD1 and the storage capacity element of the storage capacitor. Due to this, substantially, it becomes possible to realize a broader dynamic range and higher frame rate.

Abstract: A solid-state imaging device where when the charge from a photodiode PD11 is small, all of the charge is transferred to the feedback capacitor to obtain an output voltage amplified with a high gain due to a mirror effect created by a CTIA circuit including an amplifier arranged in a readout circuit and a feedback capacitor, while when the CTIA circuit is saturated, due to automatic reduction of the mirror effect, the remaining excessive charge is moved to a floating diffusion FD11 having a larger capacitance to obtain an output voltage amplified with a low gain and where the obtained voltage is simultaneously output from the pixel and taken into a column sampling circuit. Due to this, a low-luminance signal can be read out with a high gain, a high-luminance signal can be read out with a low gain suppressing saturation, and in addition, signals of a high gain and low gain can be obtained by two reading operations. Further, it becomes possible to improve the lowest object illuminance performance.

Abstract: A solid-state imaging device comprised of a first substrate on which a pixel part is formed and a second substrate on which a column readout circuit is formed along a column level connection part, a row driver is formed along a row level connection part, and a pitch conversion-use interconnect region including a slanted interconnect for pitch conversion among interconnects is formed, the pitch conversion-use interconnect region is formed at least between the end part of the column readout circuit having a third pitch shorter than the pixel part and the end part of the column level connection part and/or between the end part of the row driver having a fourth pitch shorter than the pixel part and the end part of the row level connection part.

Abstract: A solid-state imaging device which, in a voltage mode, simultaneously samples the pixel signal in all the pixels in a signal holding part serving as the pixel signal storage part, reads converted signals corresponding to readout signals held in a first signal holding capacitor and a second signal holding capacitor to a first signal line, reads converted signals corresponding to readout reset signals simultaneously in parallel to the second signal line, and supplies the same as a differential signal to a column readout circuit. Due to this, a sufficiently low parasitic light sensitivity corresponding to the application can be realized, settling error can be suppressed, and pixel fixed pattern noise can be reduced.

Abstract: A pixel portion includes a first pixel array in which a plurality of photoelectric conversion reading parts of first pixels are arranged in a matrix, a holding part array in which a plurality of signal holding parts of first pixels are arranged in a matrix, and a second pixel array in which a plurality of photoelectric conversion reading parts of second pixels are arranged in a matrix, wherein, at the time of a rolling shutter mode, readout signals of the photoelectric conversion reading parts of the first pixels and the second pixels are immediately output to a first vertical signal line without following a bypass route and, at the time of a global shutter mode, held signals of the signal holding parts of the first pixels are output to a second vertical signal line. Due to this, a solid-state imaging device can prevent complication of the configuration.

Abstract: A solid-state imaging device where when the charge from a photodiode PD11 is small, all of the charge is transferred to the feedback capacitor to obtain an output voltage amplified with a high gain due to a mirror effect created by a CTIA circuit including an amplifier arranged in a readout circuit and a feedback capacitor, while when the CTIA circuit is saturated, due to automatic reduction of the mirror effect, the remaining excessive charge is moved to a floating diffusion FD11 having a larger capacitance to obtain an output voltage amplified with a low gain and where the obtained voltage is simultaneously output from the pixel and taken into a column sampling circuit. Due to this, a low-luminance signal can be read out with a high gain, a high-luminance signal can be read out with a low gain suppressing saturation, and in addition, signals of a high gain and low gain can be obtained by two reading operations. Further, it becomes possible to improve the lowest object illuminance performance.

Abstract: Provided is a signal readout circuit including: a first capacitor that holds a first electric charge; a second capacitor that holds a second electric charge; an amplifier section including an amplifier having first and second input terminals and first and second output terminals, outputting a first potential input to the first input terminal to the first output terminal with a gain of 1 and outputting a second potential input to the second input terminal to the second output terminal with a gain of 1; and a switch circuit that switches on/off state of a connection of a terminal of the first or second capacitor with at least one of the first and second input terminals and the first and second output terminals of the amplifier, wherein a difference between the first electric charge and the second electric charge is an amount indicating a voltage value of a predetermined voltage signal.

Abstract: A solid-state image pickup device has a first substrate and a second substrate in which circuit elements constituting pixels are arranged. The pixel includes: a pixel section that includes a photoelectric conversion element; a ground potential controller that switches a potential to which a circuit element included in the pixel section is grounded; and a reading section that outputs a signal corresponding to the signal charge as a pixel signal output by the pixel. The pixel section includes: the photoelectric conversion element; an amplification transistor that outputs an amplification signal amplified according to the signal charge generated by the photoelectric conversion element; and a switch circuit that switches a ground of the amplification transistor according to a first output mode and a second output mode. The ground potential controller supplies a first potential in the first output mode and supplies a second potential in the second output mode.

Abstract: Provided is a signal readout circuit including: a first capacitor that holds a first electric charge; a second capacitor that holds a second electric charge; an amplifier section including an amplifier having first and second input terminals and first and second output terminals, outputting a first potential input to the first input terminal to the first output terminal with a gain of 1 and outputting a second potential input to the second input terminal to the second output terminal with a gain of 1; and a switch circuit that switches on/off state of a connection of a terminal of the first or second capacitor with at least one of the first and second input terminals and the first and second output terminals of the amplifier, wherein a difference between the first electric charge and the second electric charge is an amount indicating a voltage value of a predetermined voltage signal.

Abstract: A solid-state image pickup device has a first substrate and a second substrate in which circuit elements constituting pixels are arranged. The pixel includes: a pixel section that includes a photoelectric conversion element; a ground potential controller that switches a potential to which a circuit element included in the pixel section is grounded; and a reading section that outputs a signal corresponding to the signal charge as a pixel signal output by the pixel. The pixel section includes: the photoelectric conversion element; an amplification transistor that outputs an amplification signal amplified according to the signal charge generated by the photoelectric conversion element; and a switch circuit that switches a ground of the amplification transistor according to a first output mode and a second output mode. The ground potential controller supplies a first potential in the first output mode and supplies a second potential in the second output mode.

Abstract: A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.

Abstract: An imager includes a successive approximation analog-to-digital converter (SA-ADC) and an arithmetic memory. The successive approximation analog-to-digital converter converts analog representations of pixel reset and image signals for a pixel to digital representations of the pixel reset and image signals. The arithmetic memory generates a difference signal that represents the difference between the digital representations of the pixel reset signal and the pixel image signal using a most-significant-bit-first (MSB-first) calculation.

Abstract: An imager includes a successive approximation analog-to-digital converter (SA-ADC) and an arithmetic memory. The successive approximation analog-to-digital converter converts analog representations of pixel reset and image signals for a pixel to digital representations of the pixel reset and image signals. The arithmetic memory generates a difference signal that represents the difference between the digital representations of the pixel reset signal and the pixel image signal using a most-significant-bit-first (MSB-first) calculation.

Abstract: An imager device having a varied bus bit width in the image processing data-path. The imager device has a high accuracy output irrespective of digital gain value. The imager device can be adopted for all sensors that have column fixed pattern noise correction and digital gain in their data-path block.