Patents by Inventor Toshio Hamano

Toshio Hamano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6333564
    Abstract: A semiconductor device and a method of producing the same, the device including a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between the substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for the holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: December 25, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshitsugu Katoh, Mitsutaka Sato, Hiroshi Inoue, Seiichi Orimo, Akira Okada, Yoshihiro Kubota, Mitsuo Abe, Toshio Hamano, Yoshitaka Aiba, Tetsuya Fujisawa, Masaaki Seki, Noriaki Shiba
  • Publication number: 20010052653
    Abstract: A semiconductor device and a method of producing the semiconductor device are provided. This semiconductor device includes a semiconductor chip, a printed wiring board, a heat spreader, a sealing resin, and solder balls. The printed wiring board is provided with the solder balls on an outer portion and a wiring layer on an inner portion. Wires are bonded to the wiring layer, and an opening is formed in the center of the printed wiring board. The heat spreader is bonded to the printed wiring board, with the semiconductor chip being thermally connected to the stage portion of the heat spreader. The sealing resin is made up of a first sealing resin portion and a second sealing resin portion. The first and second sealing resin portions sandwich the heat spreader.
    Type: Application
    Filed: July 13, 2001
    Publication date: December 20, 2001
    Inventors: Mitsuo Abe, Yoshihiro Kubota, Yoshitsugu Katoh, Michio Hayakawa, Ryuji Nomoto, Mitsutaka Sato, Seiichi Orimo, Hiroshi Inoue, Toshio Hamano
  • Patent number: 6307259
    Abstract: According to the present invention, for a multi-layer plastic package having bonding pads at multiple levels, a plurality of electrically independent side wall conductive layers can be provided by forming side wall conductive layer on the side wall of an opening in each insulating layer. In particular, when the insulating layer forms a multi-layer structure, side wall conductive layers are formed on each of the individual side walls of the multi insulating layers, and a pre-impregnated layer is inserted between each two insulation layers, so that a plurality of electrically independent side wall conductive layers can be provided. Even for an insulating layer having a single layer structure, side wall conductive layers are formed so as to be electrically separated from each other, so that a plurality of side wall conductive layers can be provided.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: October 23, 2001
    Assignee: Fujitsu Limited
    Inventors: Kenji Asada, Toshio Hamano, Mitsuo Abe
  • Patent number: 6288444
    Abstract: A semiconductor device and a method of producing the semiconductor device are provided. This semiconductor device includes a semiconductor chip, a printed wiring board, a heat spreader, a sealing resin, and solder balls. The printed wiring board is provided with the solder balls on an outer portion and a wiring layer on an inner portion. Wires are bonded to the wiring layer, and an opening is formed in the center of the printed wiring board. The heat spreader is bonded to the printed wiring board, with the semiconductor chip being thermally connected to the stage portion of the heat spreader. The sealing resin is made up of a first sealing resin portion and a second sealing resin portion. The first and second sealing resin portions sandwich the heat spreader.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: September 11, 2001
    Assignee: Fujitsu Limited
    Inventors: Mitsuo Abe, Yoshihiro Kubota, Yoshitsugu Katoh, Michio Hayakawa, Ryuji Nomoto, Mitsutaka Sato, Seiichi Orimo, Hiroshi Inoue, Toshio Hamano
  • Patent number: 6235997
    Abstract: An LSI package including an area for mounting an LSI device thereon and a plurality of lines for connecting the LSI device and external terminals. At least two of the plurality of lines, in which differential signals are transmitted and are adjacent to each other in the LSI package, have equal lengths.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: May 22, 2001
    Assignee: Fujitsu Limited
    Inventors: Kenji Asada, Yoshihiko Ikemoto, Toshio Hamano
  • Patent number: 6184133
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 6165819
    Abstract: A method of producing a semiconductor device includes a device body producing step, electrically coupling leads and a semiconductor chip, and producing a device body by encapsulating the semiconductor chip by a resin package so that portions of the leads are exposed from the resin package, a honing step, carrying out a honing process using a polishing solution at least with respect to a resin flash adhered on the portions of the leads exposed from the resin package, an etching step, removing an unwanted stacked layer structure formed on the leads by carrying out an etching process after the honing step, and a plating step, carrying out a plating process with respect to the leads after the etching step to form a plated layer made of a soft bonding material. The honing step removes a portion of the unwanted stacked layer structure in addition to the resin flash.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: December 26, 2000
    Assignee: Fujitsu Limited
    Inventors: Masaaki Seki, Katsuhiro Hayashida, Mitsutaka Sato, Toshio Hamano
  • Patent number: 6094356
    Abstract: A semiconductor device including a semiconductor chip, connection parts arranged along one end of the semiconductor chip, and external connection terminals connected to the connection parts.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: July 25, 2000
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Kazuhiko Mitobe, Katsuhiro Hayashida, Masaaki Seki, Seiichi Orimo, Toshio Hamano
  • Patent number: 6088233
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: July 11, 2000
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 5978222
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: November 2, 1999
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 5923540
    Abstract: A semiconductor device has an electrical circuit and a grounding terminal. A multilayer substrate has a plurality of insulator layers and conductor layers in a stacked arrangement and a surface with first and second regions, the conductor layers making electrical contact with the electrical circuit and the grounding terminal of the semiconductor device. The first region generally surrounds the semiconductor device and has first connecting conductors penetrating at least a part of the multilayer substrate so that each of the first conductors makes contact with one or a plurality of corresponding conductor layers. The second region generally surrounds the first region and has second connecting conductors penetrating at least a part of the multilayer substrate and only making contact with one or a plurality of conductor layers coupled to the grounding terminal of the semiconductor device.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: July 13, 1999
    Assignee: Fujitsu Limited
    Inventors: Kenji Asada, Toshio Hamano, Masaru Nukiwa
  • Patent number: 5804468
    Abstract: A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: September 8, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
  • Patent number: 5729435
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, and an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths. The semiconductor device further includes a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a passage restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: March 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 5497032
    Abstract: A semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: March 5, 1996
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
  • Patent number: 5407502
    Abstract: A method is provided wherein semiconductor device includes a package, a semiconductor chip provided on the package, an intermediate layer formed on the package, an adhesive layer formed on the intermediate layer, and a lid formed on the adhesive layer and sealing the semiconductor chip. The intermediate layer contains a major component which is the same as a major component of the package. The method includes screen printing the intermediate layer on a predetermined area of the package and the formation of a roughened surface by sintering the intermediate layer. The major component comprises, among other materials, alumina or alumina and glass.
    Type: Grant
    Filed: September 16, 1993
    Date of Patent: April 18, 1995
    Assignee: Fujitsu Limited
    Inventors: Takeshi Takenaka, Toshio Hamano, Takekiyo Saito
  • Patent number: 5278429
    Abstract: A semiconductor device includes a package, a semiconductor chip provided on the package, an intermediate layer formed on the package, an adhesive layer formed on the intermediate layer, and a lid formed on the adhesive layer and sealing the semiconductor chip. The intermediate layer contains a major component which is the same as a major component of the package.
    Type: Grant
    Filed: April 20, 1993
    Date of Patent: January 11, 1994
    Assignee: Fujitsu Limited
    Inventors: Takeshi Takenaka, Toshio Hamano, Takekiyo Saito
  • Patent number: 5092568
    Abstract: A coil spring device comprises a coil spring formed of a spiral wire having a first end and a second end, a first end support mechanism supporting the first end of the wire, and a second end support mechanism supporting the second end of the wire. The paired support mechanisms are movable relatively to each other in the axial direction of the coil spring. The first support mechanism supports the first end of the wire for rotation only around a first diametrical axis which extends toward a coil central axis. The second support mechanism supports the second end of the wire for rotation only around a second diametrical axis which extends toward the central axis.
    Type: Grant
    Filed: March 19, 1990
    Date of Patent: March 3, 1992
    Assignee: NHK Spring Co., Ltd.
    Inventors: Toshihiro Tachikawa, Toshio Hamano
  • Patent number: 4999319
    Abstract: A method of manufacturing a semiconductor device having a package structure including a lead base and a cap includes the steps of fixing a semiconductor chip to a lead base, and placing a fixation pellet in a cap, the fixation pellet being made of a material which melts and is subsequently hardened by a rise in temperature. The lead base carrying the semiconductor chip upside-down on the fixation pellet is placed in the cap. The fixation pellet between the cap and the lead base carrying the semiconductor chip is then heated to melt the fication pellet and subsequently harden the melted fixation pellet. Thus, the lead base carrying the semiconductor chip is fixed to the cap to form a package structure.
    Type: Grant
    Filed: April 6, 1989
    Date of Patent: March 12, 1991
    Assignee: Fujitsu Limited
    Inventors: Toshio Hamano, Shigeo Natsume
  • Patent number: 4626960
    Abstract: A semiconductor device including a ceramic base having a cavity carrying a semiconductor chip, and a ceramic cap covering and sealing the ceramic base. The cap has a metallization pattern covering not only a region where it contacts the base but also the four side surfaces of the cap, which is provided in order to prevent flow or flying out of excess solder toward the outside of the cap and the base and into the cavity.
    Type: Grant
    Filed: November 28, 1984
    Date of Patent: December 2, 1986
    Assignee: Fujitsu Limited
    Inventors: Toshio Hamano, Kaoru Tachibana, Hideji Aoki