Patents by Inventor Toshio Kobayashi
Toshio Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140313681Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
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Patent number: 8823097Abstract: A transistor-type protection device includes: a semiconductor substrate; a well of a first-conductivity-type formed in the semiconductor substrate; a source region of a second-conductivity-type formed in the well; a gate electrode formed on the well via a gate insulating film at one side of the source region; plural drain regions of a second-conductivity-type formed apart from each other and respectively separated at a predetermined distance from a well part immediately below the gate electrode film; and a resistive connection part connecting between the plural drain regions with a predetermined electric resistance.Type: GrantFiled: November 18, 2009Date of Patent: September 2, 2014Assignee: Sony CorporationInventors: Tsutomu Imoto, Toshio Kobayashi
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Patent number: 8793868Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: GrantFiled: June 23, 2011Date of Patent: August 5, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Publication number: 20130337125Abstract: In a raw material preparing step, a rice powder as a primary raw material powder is added with a water to prepare a mixed raw material. In a kneading step, the mixed raw material is kneaded to form a kneaded substance. In a pressing/extending step, the kneaded substance is pressed and extended to form noodle dough sheet. In a slitting step, the noodle dough sheet is slit into predetermined noodle strand shape to obtain a continuous noodle strand However, these steps maintain a non-alpha state of the rice powder component In a packaging step, a unit-length noodle strand is accommodated in a pouch-like heat-resistant packaging container and hermetically sealed to obtain a packaged unit-length noodle strand, while maintaining a non-alpha state of the rice powder component in the noodle strand.Type: ApplicationFiled: June 14, 2012Publication date: December 19, 2013Applicant: KOBAYASHI NOODLE CO., LTD.Inventor: Toshio Kobayashi
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Publication number: 20130313267Abstract: The present invention provides a refrigerator with improved refrigerator box strength and high heat insulating performance, which is configured such that external deformation due to entry of air into a vacuum heat insulating material, the entry of air being caused by aging degradation, is prevented. The present invention includes: a heat-insulated box including an inner casing and an outer casing, in which space between the inner casing and the outer casing is filled with a foamed heat insulating material; and a vacuum heat insulating material disposed in at least a side wall of the heat-insulated box together with the foamed heat insulating material, the vacuum heat insulating material including an outer skin material, the outer skin material including at least a core material and being decompression-sealed. The vacuum heat insulating material includes a gas adsorbent.Type: ApplicationFiled: August 31, 2012Publication date: November 28, 2013Applicant: PANASONIC CORPORATIONInventors: Yoshimasa Horio, Shinya Nagahata, Toshio Kobayashi, Tarou Yamaguchi, Shuhei Sugimoto, Kazuya Nakanishi, Junichi Kurita, Hiroki Hamano, Shinya Kojima, Noriyuki Miyaji
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Publication number: 20130277701Abstract: A package for mounting a light emitting element includes a housing and a flat plate-shaped electrode. The electrode is exposed from a lower surface of the housing. An upper surface of the electrode includes a mounting area on which the light emitting element is mounted. An insulator is arranged on the upper surface of the electrode. An element connector is connected to the insulator. A tubular reflective portion extends from the element connector to a height corresponding to the upper surface of the housing. A terminal is arranged on the side surface of the housing and connected to the reflective portion. A recess accommodates the light emitting element. The recess is formed in an upper portion of the housing, and the recess is formed by the upper surface of the electrode, the element connector, and the reflective portion.Type: ApplicationFiled: April 17, 2013Publication date: October 24, 2013Applicant: Shinko Electric Industries Co., Ltd.Inventors: Toshiyuki Okabe, Tsuyoshi Kobayashi, Toshio Kobayashi, Yasuyuki Kimura
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Publication number: 20130280451Abstract: A paste-like thermally foaming filler contains 2 to 20 parts by weight of an uncrosslinked synthetic rubber. 5 to 30 parts by weight of a partially crosslinked rubber, 0.1 to 5 parts by weight of a quinone-based vulcanizing agent, 0.2 to 1 parts by weight of thermally expandable balloons, 1 to 10 parts by weight of a thermoplastic resin, 20 to 50 parts by weight of a plasticizer, 15 to 50 parts by weight of an inorganic filler, and 2 to 15 parts by weight of a chemical foaming agent. The paste-like thermally foaming filler exhibits high foaming capability even at low temperatures.Type: ApplicationFiled: October 5, 2011Publication date: October 24, 2013Applicant: SUNSTAR ENGINEERING INC.Inventors: Toshio Kobayashi, Junji Kono, Yutaka Sugiura
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Patent number: 8482117Abstract: An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via.Type: GrantFiled: July 13, 2011Date of Patent: July 9, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazutaka Kobayashi, Tadashi Arai, Toshio Kobayashi
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Patent number: 8379401Abstract: There is provided a wiring board. The wiring board includes: a plurality of laminated insulating layers including a first insulating layer, the first insulating layer being either one of an uppermost layer or a lowermost layer; wiring patterns formed in the plurality of insulating layers; external connection pads provided on the first insulating layer; external connection terminals provided on the external connection pads; and a molding resin provided on a surface of the first insulating layer on which the external connection pads are provided, the molding resin having openings from which the external connection pads are exposed. A thickness of the molding resin is set such that the molding resin does not protrude above the external connection terminals.Type: GrantFiled: August 22, 2008Date of Patent: February 19, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Toshio Kobayashi
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Patent number: 8256530Abstract: An object is to provide a method capable of boring a borehole even when quartz glass or silicon dioxide is deposited as molten dross by laser irradiation. A laser irradiation position of a workpiece is irradiated with a laser having wavelength of 1.2 ?m or longer and a high factor of absorption into liquid, for example, a CO2 laser, from a laser oscillator through liquid. By high pressure generated in an advancing microbubble flow occurring in the liquid, molten dross is scattered. Thus, the processing, such as boring, of the rock is performed.Type: GrantFiled: December 18, 2007Date of Patent: September 4, 2012Assignees: Japan Drilling Co., Ltd., Tohoku University, Japan Oil, Gas and Metals National CorporationInventors: Toshio Kobayashi, Kazuyoshi Takayama, Kiyonobu Ohtani, Satoru Umezu
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Patent number: 8232639Abstract: In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.Type: GrantFiled: November 23, 2010Date of Patent: July 31, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshio Kobayashi, Takaharu Yamano, Takashi Kurihara
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Publication number: 20120153507Abstract: A method include disposing a semiconductor chip having an electrode pad formed on a circuit forming surface on one surface of a support so that the electrode pad contacts with the one surface of the support, forming a first insulating layer on the one surface of the support so that the first insulating layer covers at least a side surface of the semiconductor chip, removing the support and forming an interconnection terminal on the electrode pad, forming a second insulating layer on the circuit forming surface of the semiconductor chip and the first insulating layer so that the second insulating layer covers the interconnection terminal, exposing an end portion of the interconnection terminal from a top surface of the second insulating layer, and forming a wiring pattern that is electrically connected to the end portion of the interconnection terminal, on the top surface of the second insulating layer.Type: ApplicationFiled: December 20, 2011Publication date: June 21, 2012Applicant: Shinko Electric Industries Co., Ltd.Inventors: Syota MIKI, Takaharu Yamano, Toshio Kobayashi
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Patent number: 8164131Abstract: A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on the channel formation region; and a control electrode formed on the laminated insulating film. The laminated insulating film includes a first insulating film, a charge storage film, and a second insulating film in order from the channel formation region side. The control electrode extends to above one of the second semiconductor region and the third semiconductor region. The charge storage film present between an extended portion of the control electrode and the second semiconductor region or the third semiconductor region is removed and a portion where the charge storage film is removed is filled with a third insulating film.Type: GrantFiled: December 4, 2006Date of Patent: April 24, 2012Assignee: Sony CorporationInventors: Toshio Kobayashi, Saori Hara
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Publication number: 20120013021Abstract: An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via.Type: ApplicationFiled: July 13, 2011Publication date: January 19, 2012Applicant: Shinko Electric Industries Co., LTD.Inventors: Kazutaka Kobayashi, Tadashi Arai, Toshio Kobayashi
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Publication number: 20110256662Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: ApplicationFiled: June 23, 2011Publication date: October 20, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
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Patent number: 7989707Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: GrantFiled: December 12, 2006Date of Patent: August 2, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Patent number: 7985619Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer.Type: GrantFiled: October 29, 2009Date of Patent: July 26, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshio Kobayashi, Tadashi Arai, Takaharu Yamano
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Patent number: 7981724Abstract: A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer; a sixth step of mounting a wiring substrate on a surface of each of the semiconductor device and the second insulating layer; a seventh step of forming a via-hole in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern on a surface of each of the first insulating layer and the second insulating layer.Type: GrantFiled: October 29, 2009Date of Patent: July 19, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshio Kobayashi, Tadashi Arai, Takaharu Yamano
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Publication number: 20110165367Abstract: A plurality of thin-wall parts (9a) of a sealant layer (7) are formed in a portion continuously changed in the interval of one sealing part (8) and a gas barrier layer (6) of other laminate film (4). At the inner circumferential side between the adjacent thin-wall parts (9a) and the thin-wall part (9a) at the innermost circumferential side and at the outer circumferential side of the thin-wall part (9a) of the outermost circumferential side, a thick-wall part (9b) of the sealant layer (7) is formed. All of the opposing sealant layers (7) between the two adjacent thin-wall parts (9a) are mutually heated and fused, so that an excellent adiabatic performance is maintained for a long period.Type: ApplicationFiled: September 9, 2009Publication date: July 7, 2011Applicant: Panasonic CorporationInventors: Shinya Kojima, Fumie Horibata, Tomohisa Tenra, Toshio Kobayashi
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Publication number: 20110127656Abstract: In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.Type: ApplicationFiled: November 23, 2010Publication date: June 2, 2011Inventors: Toshio KOBAYASHI, Takaharu YAMANO, Takashi KURIHARA