Abstract: A rotor of a motor is attached to a rotor axis slidably both in axial direction and rotational direction, each of elastic bodies is attached to each of side faces of the rotor, and the rotor is fastened to the rotor axis through the elastic body, mechanically by applying pressure on each of the side faces of the rotor in the axial direction through the elastic body, or chemically by bonding the rotor axis and each of the elastic bodies as well as each of the elastic bodies and each of the corresponding side faces of the rotor.

Abstract: Disclosed is a coating composition for PC tendon, which is applied on surface of the PC tendon. This composition includes epoxy resin, multifunctional isocyanate compound, calcium oxide and water, and further includes water-absorbing polymer as necessary. A curing time thereof is adjusted so that tensioning by the PC tendon can be exerted 30 days or later after casting of the concrete. Accordingly, even when applied to a massive concrete structure, the coating composition enables effective tensioning after hardening of the concrete, while exhibiting excellent storage stability.

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract: To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2).

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2).

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: An elastically stretchable nonwoven fabric including thermoplastic elastomer filaments; the filaments being heat-sealed and/or mechanically intertwined together to form the nonwoven fabric that has crimped regions and non-crimped regions wherein each of the crimped regions has fine crimps in the rate of 50/cm or higher.

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract: An apparatus for producing a web of continuous fibers having a melt extruder, an endless belt running in one direction and a guide box located between the extruder and the belt. The guide box has front and rear walls as viewed in the running direction of the belt, a pair of side walls extending between the front and rear walls and upper and lower end openings. The fibers extruded from the extruder enter the upper end opening by suction exerted in the vicinity of the lower end opening. The guide box is formed in the front wall and/or the rear wall with intermediate opening(s) serving to introduce the outside air into the guide box.

Abstract: A method for boring a well with a laser beam is provided, the method comprising: shining the laser beam into a conduit, wherein the laser beam is guided through the conduit by the internal reflectivity of said conduit; and extending the conduit into the well, so that the laser beam exiting the conduit shines onto an area in the well to be bored. A system for boring a well with a laser beam is also provided, the system comprising: a means for shining the laser beam into a conduit; wherein the laser beam is guided through the conduit by the internal reflectivity of said conduit; and a means for extending the conduit into the well, so that the laser beam exiting the conduit shines onto an area in the well to be bored. An apparatus is provided as well, comprising a conduit that is extendable into the well, and an inner surface inside of the conduit, wherein the inner surface is reflective to the laser beam.

Abstract: A terminal arrangement of a motor has a terminal base formed with a plurality of terminal pins, the terminal base being fixed detachably on a stator iron core of a motor, terminal pins formed on bobbins, connected electrically with windings wound around the bobbins, a printed circuit board arranged on the stator iron core so as to connect electrically the terminal pins formed on the bobbins with the terminal pins formed on the terminal base, and an end bracket arranged so as to cover the printed circuit board. A hole is formed in the stator iron core, and an earth electrode is projected from the terminal base, and inserted into the hole so as to be connected electrically with the stator iron core, the earth electrode being connected electrically to one of the terminal pins formed on the terminal base. A capacitor motor has a motor having a stator iron core, and a phase advancing capacitor fixed detachably on the stator iron core.

Abstract: A sputtering apparatus is provided with a DC power supply 1, an inverter 2 that converts DC voltage to AC voltage, a matching circuit 10 that transforms the AC voltage, a rectifier 4 that that converts the transformed AC voltage to direct current, and a sputtering load 6. The matching circuit 10 has a transformer 3 that transforms AC voltage from the inverter 2, inductance L provided in series with at least one of the primary winding 31 and secondary winding 32, and a condenser C provided in parallel with at least one of the primary winding 31 and secondary winding 32 through inductance L.

Abstract: An automatic transmission has concentric first and second input shafts, and a parallel output shaft. A plurality of transmission gear trains are provided between the input shafts and the output shaft. An input switching shaft is arranged in parallel with the input shafts and the output shaft, and is provided with a first friction clutch switch switches into a power transmission state and a disconnection state with respect to the first input shaft, and a second friction clutch which switches into a power transmission state and a disconnection state with respect to the second input shaft. Engine power is bypassed to the input switching shaft so as to be transmitted to the output shaft via the first friction clutch or the second friction clutch and to effectively shorten the entire length of the transmission.

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: An apparatus and process for making an elastic composite sheet including a pair of rolls adapted to bond respective surfaces of a inelastic sheet and a elastic sheet and fed together into a nip of the rolls. One of the rolls is formed with ridges while the other roll is formed with grooves and the ridges are engaged with the grooves with spaces left between surfaces of the ridges and the grooves to form the inelastic sheet on its surface with stripe-like crests and flat troughs each defined between each pair of the adjacent crests; and the inelastic sheet is bonded along its troughs to the surface of the elastic sheet.